Wesley W. Terpstra bff0ffa428 tilelink2 RegisterRouter: fix output data glitches ... If a device changes a register while it's being read but not yet accepted, this an lead to 'data' changing while 'valid' is high. A violation. The problem is that RegMapper is fundamentally DecoupledIO. So fix it with a Queue.		2016-10-02 02:24:02 -07:00
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main/scala	tilelink2 RegisterRouter: fix output data glitches	2016-10-02 02:24:02 -07:00