7c0c48fac4
We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
77 lines
2.3 KiB
Plaintext
77 lines
2.3 KiB
Plaintext
#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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$(generated_dir)/consts.$(CONFIG).vh \
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$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
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$(base_dir)/vsrc/$(TB).v \
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$(base_dir)/vsrc/backup_mem.v \
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/vcs_main.$(TB).cc \
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$(base_dir)/csrc/mm.cc \
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$(base_dir)/csrc/mm_dramsim2.cc \
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#--------------------------------------------------------------------
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# Build Verilog
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#--------------------------------------------------------------------
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verilog: $(sim_vsrcs)
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.PHONY: verilog
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-I$(realpath $(base_dir))/dramsim2" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
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-CC "-include $(scr_header)" \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).verbose \
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+libext+.v \
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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-debug_pp \
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simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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