144 lines
5.4 KiB
Scala
144 lines
5.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.tilelink2
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import Chisel._
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import config._
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import diplomacy._
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import regmapper._
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import scala.math.{min,max}
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class TLRegisterNode(
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address: AddressSet,
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device: Device,
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deviceKey: String = "reg",
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concurrency: Int = 0,
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beatBytes: Int = 4,
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undefZero: Boolean = true,
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executable: Boolean = false)
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extends TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(address),
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resources = Seq(Resource(device, deviceKey)),
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle
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{
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require (address.contiguous)
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// Calling this method causes the matching TL2 bundle to be
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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val a = bundleIn(0).a
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val d = bundleIn(0).d
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val edge = edgesIn(0)
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// Please forgive me ...
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val baseEnd = 0
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val (sizeEnd, sizeOff) = (edge.bundle.sizeBits + baseEnd, baseEnd)
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val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
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val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
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val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, addrLoEnd)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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in.bits.read := a.bits.opcode === TLMessages.Get
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in.bits.index := edge.addr_hi(a.bits)
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in.bits.data := a.bits.data
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in.bits.mask := a.bits.mask
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in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
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// Invoke the register map builder
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val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
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// No flow control needed
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in.valid := a.valid
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a.ready := in.ready
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d.valid := out.valid
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out.ready := d.ready
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// We must restore the size and addr_lo to enable width adapters to work
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d.bits := edge.AccessAck(
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fromAddress = out.bits.extra(addrLoEnd-1, addrLoOff),
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fromSink = UInt(0), // our unique sink id
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toSource = out.bits.extra(sourceEnd-1, sourceOff),
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lgSize = out.bits.extra(sizeEnd-1, sizeOff))
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// avoid a Mux on the data bus by manually overriding two fields
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d.bits.data := out.bits.data
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d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
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// Tie off unused channels
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bundleIn(0).b.valid := Bool(false)
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bundleIn(0).c.ready := Bool(true)
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bundleIn(0).e.ready := Bool(true)
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}
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}
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object TLRegisterNode
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{
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def apply(
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address: AddressSet,
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device: Device,
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deviceKey: String = "reg",
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concurrency: Int = 0,
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beatBytes: Int = 4,
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undefZero: Boolean = true,
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executable: Boolean = false) =
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new TLRegisterNode(address, device, deviceKey, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a TL2
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// register mapped device from a totally abstract register mapped device.
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// See GPIO.scala in this directory for an example
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abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val device = new SimpleDevice(devname, devcompat)
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val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable)
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val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
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}
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case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters)
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class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
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{
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implicit val p = arg.p
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val interrupts = arg.interrupts
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val in = arg.in
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}
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class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
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class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
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extends LazyModuleImp(router) with HasRegMap
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{
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val io = bundleBuilder
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val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
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val address = router.address
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def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
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}
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class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp](
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val base: BigInt,
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val devname: String,
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val devcompat: Seq[String],
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val interrupts: Int = 0,
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val size: BigInt = 4096,
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val concurrency: Int = 0,
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val beatBytes: Int = 4,
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val undefZero: Boolean = true,
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val executable: Boolean = false)
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(bundleBuilder: TLRegBundleArg => B)
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(moduleBuilder: (=> B, TLRegisterRouterBase) => M)(implicit p: Parameters)
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extends TLRegisterRouterBase(devname, devcompat, AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
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{
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require (isPow2(size))
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// require (size >= 4096) ... not absolutely required, but highly recommended
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lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
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}
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