216 lines
7.3 KiB
Scala
216 lines
7.3 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import rocket._
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import diplomacy._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.converters._
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import util._
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import coreplex._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import scala.collection.immutable.HashMap
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config(
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topDefinitions = {
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val edgeDataBits = site(EdgeDataBits)
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lazy val edgeDataBeats = (8 * site(CacheBlockBytes)) / edgeDataBits
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pname match {
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//Memory Parameters
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case EdgeDataBits => 64
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case EdgeIDBits => 5
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case NastiKey => NastiParameters(
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dataBits = edgeDataBits,
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addrBits = site(PAddrBits),
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idBits = site(EdgeIDBits))
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case TLEmitMonitors => true
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case TLKey("EdgetoSlave") =>
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site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
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case TLKey("MCtoEdge") =>
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site(TLKey("L2toMC")).copy(dataBeats = edgeDataBeats)
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case TLKey("MMIOtoEdge") =>
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site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
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case NExtTopInterrupts => 2
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case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
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// Note that PLIC asserts that this is > 0.
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = edgeDataBits)
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => LazyModule(new ExampleTop(new DefaultCoreplex()(_))(p))
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case SimMemLatency => 0
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case _ => throw new CDEMatchError
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}
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}
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})
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BaseConfig)
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case _ => throw new CDEMatchError
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}
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)
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(
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new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
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class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
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class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualBankL2Config extends Config(
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new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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class DualChannelL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelDualBankConfig extends Config(
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualChannelDualBankL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
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new WithL2Cache ++ new BaseConfig)
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class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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class WithEdgeDataBits(dataBits: Int) extends Config(
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(pname, site, here) => pname match {
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case EdgeDataBits => dataBits
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case _ => throw new CDEMatchError
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})
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class Edge128BitConfig extends Config(
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new WithEdgeDataBits(128) ++ new BaseConfig)
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class Edge32BitConfig extends Config(
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new WithEdgeDataBits(32) ++ new BaseConfig)
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class SmallL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Capacity(256) ++ new DefaultL2Config)
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class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
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class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
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class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
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class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
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class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
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class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
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class DualCoreConfig extends Config(
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new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
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class TinyConfig extends Config(
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new WithScratchpads ++
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new WithSmallCores ++ new WithRV32 ++
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new WithStatelessBridge ++ new BaseConfig)
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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case _ => throw new CDEMatchError
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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case _ => throw new CDEMatchError
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}
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)
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class WithNoPeripheryArithAMO extends Config (
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(pname, site, here) => pname match {
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
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}
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)
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class With64BitPeriphery extends Config (
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(pname, site, here) => pname match {
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
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}
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)
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class WithTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => true
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case _ => throw new CDEMatchError
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}
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)
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class WithoutTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => false
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case _ => throw new CDEMatchError
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}
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)
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class WithNExtTopInterrupts(nExtInts: Int) extends Config(
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(pname, site, here) => pname match {
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case NExtTopInterrupts => nExtInts
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case _ => throw new CDEMatchError
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}
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)
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class WithNBreakpoints(hwbp: Int) extends Config (
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(pname,site,here) => pname match {
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case NBreakpoints => hwbp
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case _ => throw new CDEMatchError
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}
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)
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