242 lines
6.4 KiB
Scala
242 lines
6.4 KiB
Scala
package rocket
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import Chisel._
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import scala.math._
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object Constants
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{
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val NTILES = 1
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val HAVE_RVC = false
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val HAVE_FPU = true
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val HAVE_VEC = false
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val MAX_THREADS =
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hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
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val HTIF_WIDTH = 16
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val MEM_BACKUP_WIDTH = HTIF_WIDTH
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val BR_X = Bits("b???", 3)
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val BR_EQ = UFix(0, 3)
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val BR_NE = UFix(1, 3)
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val BR_J = UFix(2, 3)
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val BR_N = UFix(3, 3)
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val BR_LT = UFix(4, 3)
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val BR_GE = UFix(5, 3)
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val BR_LTU = UFix(6, 3)
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val BR_GEU = UFix(7, 3)
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val PC_EX4 = UFix(0, 2)
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val PC_EX = UFix(1, 2)
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val PC_WB = UFix(2, 2)
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val PC_PCR = UFix(3, 2)
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val A2_X = Bits("b???", 3)
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val A2_BTYPE = UFix(0, 3);
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val A2_LTYPE = UFix(1, 3);
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val A2_ITYPE = UFix(2, 3);
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val A2_ZERO = UFix(4, 3);
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val A2_JTYPE = UFix(5, 3);
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val A2_RTYPE = UFix(6, 3);
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val MUL_X = Bits("b??", 2)
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val MUL_LO = UFix(0, 2);
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val MUL_H = UFix(1, 2);
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val MUL_HSU = UFix(2, 2);
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val MUL_HU = UFix(3, 2);
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val DIV_X = Bits("b??", 2)
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val DIV_D = UFix(0, 2);
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val DIV_DU = UFix(1, 2);
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val DIV_R = UFix(2, 2);
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val DIV_RU = UFix(3, 2);
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val X = Bits("b?", 1)
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val N = Bits(0, 1);
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val Y = Bits(1, 1);
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val WA_X = X
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val WA_RD = N
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val WA_RA = Y
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val WB_X = Bits("b???", 3)
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val WB_PC = UFix(0, 3);
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val WB_ALU = UFix(2, 3);
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val WB_TSC = UFix(4, 3);
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val WB_IRT = UFix(5, 3);
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val DW_X = X
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val DW_32 = N
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val DW_64 = Y
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val DW_XPR = Y
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val RA = UFix(1, 5);
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val MT_X = Bits("b???", 3);
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val MT_B = Bits("b000", 3);
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val MT_H = Bits("b001", 3);
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val MT_W = Bits("b010", 3);
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val MT_D = Bits("b011", 3);
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val MT_BU = Bits("b100", 3);
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val MT_HU = Bits("b101", 3);
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val MT_WU = Bits("b110", 3);
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val M_X = Bits("b????", 4);
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val M_XRD = Bits("b0000", 4); // int load
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val M_XWR = Bits("b0001", 4); // int store
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val M_PFR = Bits("b0010", 4); // prefetch with intent to read
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val M_PFW = Bits("b0011", 4); // prefetch with intent to write
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val M_FLA = Bits("b0100", 4); // write back and invlaidate all lines
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val M_FENCE = Bits("b0101", 4); // memory fence
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val M_INV = Bits("b0110", 4); // write back and invalidate line
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val M_CLN = Bits("b0111", 4); // write back line
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val M_XA_ADD = Bits("b1000", 4);
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val M_XA_SWAP = Bits("b1001", 4);
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val M_XA_AND = Bits("b1010", 4);
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val M_XA_OR = Bits("b1011", 4);
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val M_XA_MIN = Bits("b1100", 4);
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val M_XA_MAX = Bits("b1101", 4);
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val M_XA_MINU = Bits("b1110", 4);
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val M_XA_MAXU = Bits("b1111", 4);
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val PCR_X = Bits("b???", 3)
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val PCR_N = Bits(0,3)
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val PCR_F = Bits(1,3) // mfpcr
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val PCR_T = Bits(4,3) // mtpcr
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val PCR_C = Bits(6,3) // clearpcr
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val PCR_S = Bits(7,3) // setpcr
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val SYNC_X = Bits("b??", 2)
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val SYNC_N = Bits(0,2);
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val SYNC_D = Bits(1,2);
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val SYNC_I = Bits(2,2);
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val PCR_STATUS = UFix( 0, 5);
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val PCR_EPC = UFix( 1, 5);
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val PCR_BADVADDR = UFix( 2, 5);
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val PCR_EVEC = UFix( 3, 5);
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val PCR_COUNT = UFix( 4, 5);
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val PCR_COMPARE = UFix( 5, 5);
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val PCR_CAUSE = UFix( 6, 5);
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val PCR_PTBR = UFix( 7, 5);
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val PCR_SEND_IPI = UFix( 8, 5);
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val PCR_CLR_IPI = UFix( 9, 5);
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val PCR_COREID = UFix(10, 5);
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val PCR_IMPL = UFix(11, 5);
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val PCR_K0 = UFix(12, 5);
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val PCR_K1 = UFix(13, 5);
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val PCR_VECBANK = UFix(18, 5);
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val PCR_VECCFG = UFix(19, 5);
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val PCR_RESET = UFix(29, 5);
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val PCR_TOHOST = UFix(30, 5);
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val PCR_FROMHOST = UFix(31, 5);
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// definition of bits in PCR status reg
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val SR_ET = 0; // enable traps
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val SR_EF = 1; // enable floating point
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val SR_EV = 2; // enable vector unit
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val SR_EC = 3; // enable compressed instruction encoding
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val SR_PS = 4; // mode stack bit
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val SR_S = 5; // user/supervisor mode
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val SR_U64 = 6; // 64 bit user mode
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val SR_S64 = 7; // 64 bit supervisor mode
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val SR_VM = 8 // VM enable
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val SR_IM = 16 // interrupt mask
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val SR_IM_WIDTH = 8
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val CAUSE_INTERRUPT = 32
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val IRQ_IPI = 5
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val IRQ_TIMER = 7
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val PADDR_BITS = 40;
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val VADDR_BITS = 43;
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val PGIDX_BITS = 13;
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val PPN_BITS = PADDR_BITS-PGIDX_BITS;
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val VPN_BITS = VADDR_BITS-PGIDX_BITS;
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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// rocketNBDCache parameters
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val INST_BITS = 32
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val DCACHE_PORTS = 3
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val CPU_DATA_BITS = 64;
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val CPU_TAG_BITS = 9;
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val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS
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val OFFSET_BITS = 6; // log2(cache line size in bytes)
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val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
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val NRPQ = 16; // number of secondary misses
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val NSDQ = 17; // number of secondary stores/AMOs
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val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
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val IDX_BITS = 7;
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val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
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val NWAYS = 4
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require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
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// coherence parameters
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
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val TILE_ID_BITS = log2Up(NTILES)+1
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val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
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val NGLOBAL_XACTS = 8
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val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
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val X_INIT_TYPE_MAX_BITS = 2
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val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
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val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
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val X_INIT_ATOMIC_OP_BITS = 4
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val X_REP_TYPE_MAX_BITS = 3
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val P_REQ_TYPE_MAX_BITS = 2
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val P_REP_TYPE_MAX_BITS = 3
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// external memory interface
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val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
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val MEM_DATA_BITS = 128
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
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val BTB_ENTRIES = 8
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val ITLB_ENTRIES = 8
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val DTLB_ENTRIES = 16
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val VITLB_ENTRIES = 4
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val START_ADDR = 0x2000;
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val FPU_N = UFix(0, 1);
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val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
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val VEC_N = UFix(0, 1);
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val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N;
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val VEC_X = Bits("b??", 2).toUFix
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val VEC_FN_N = UFix(0, 2)
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val VEC_VL = UFix(1, 2)
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val VEC_CFG = UFix(2, 2)
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val VEC_CFGVL = UFix(3, 2)
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val VCMD_I = UFix(0, 3)
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val VCMD_F = UFix(1, 3)
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val VCMD_TX = UFix(2, 3)
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val VCMD_TF = UFix(3, 3)
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val VCMD_MX = UFix(4, 3)
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val VCMD_MF = UFix(5, 3)
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val VCMD_A = UFix(6, 3)
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val VCMD_X = UFix(0, 3)
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val VIMM_VLEN = UFix(0, 1)
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val VIMM_ALU = UFix(1, 1)
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val VIMM_X = UFix(0, 1)
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val VIMM2_RS2 = UFix(0, 1)
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val VIMM2_ALU = UFix(1, 1)
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val VIMM2_X = UFix(0, 1)
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val DTLB_CPU = 0
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val DTLB_VEC = 1
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val DTLB_VPF = 2
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val DMEM_CPU = 0
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val DMEM_PTW = 1
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val DMEM_VU = 2
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}
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