57 lines
2.1 KiB
Scala
57 lines
2.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore
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import Chisel._
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import diplomacy._
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package object tilelink2
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{
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type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
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type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
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def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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// Fill 1s from low bits to high bits
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def leftOR(x: UInt) = {
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val w = x.getWidth
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def helper(s: Int, x: UInt): UInt =
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if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
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helper(1, x)
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}
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// Fill 1s form high bits to low bits
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def rightOR(x: UInt) = {
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val w = x.getWidth
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def helper(s: Int, x: UInt): UInt =
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if (s >= w) x else helper(s+s, x | (x >> s))
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helper(1, x)
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}
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// This gets used everywhere, so make the smallest circuit possible ...
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def maskGen(addr_lo: UInt, lgSize: UInt, beatBytes: Int): UInt = {
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val lgBytes = log2Ceil(beatBytes)
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val sizeOH = UIntToOH(lgSize, log2Up(beatBytes))
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def helper(i: Int): Seq[(Bool, Bool)] = {
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if (i == 0) {
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Seq((lgSize >= UInt(lgBytes), Bool(true)))
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} else {
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val sub = helper(i-1)
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val size = sizeOH(lgBytes - i)
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val bit = addr_lo(lgBytes - i)
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val nbit = !bit
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Seq.tabulate (1 << i) { j =>
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val (sub_acc, sub_eq) = sub(j/2)
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val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
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val acc = sub_acc || (size && eq)
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(acc, eq)
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}
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}
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}
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Cat(helper(lgBytes).map(_._1).reverse)
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}
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}
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