113 lines
3.2 KiB
Scala
113 lines
3.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import diplomacy._
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import uncore.tilelink2._
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import unittest._
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class RRTest0(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
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new AXI4RegBundle((), _) with RRTest0Bundle)(
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new AXI4RegModule((), _, _) with RRTest0Module)
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class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
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new AXI4RegBundle((), _) with RRTest1Bundle)(
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new AXI4RegModule((), _, _) with RRTest1Module)
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class AXI4LiteFuzzRAM extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
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val xbar = LazyModule(new TLXbar)
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val gpio = LazyModule(new RRTest1(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := model.node
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ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
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gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4LiteFuzzRAMTest extends UnitTest(500000) {
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val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
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io.finished := dut.io.finished
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}
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class AXI4FullFuzzRAM extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
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val xbar = LazyModule(new TLXbar)
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val gpio = LazyModule(new RRTest0(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := model.node
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ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
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gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4FullFuzzRAMTest extends UnitTest(500000) {
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val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
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io.finished := dut.io.finished
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}
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class AXI4FuzzMaster extends LazyModule
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{
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val node = AXI4OutputNode()
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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node := TLToAXI4(4)(model.node)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val finished = Bool(OUTPUT)
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}
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4FuzzSlave extends LazyModule
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{
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val node = AXI4InputNode()
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
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ram.node := TLFragmenter(4, 16)(AXI4ToTL()(AXI4Fragmenter()(node)))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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class AXI4FuzzBridge extends LazyModule
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{
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val master = LazyModule(new AXI4FuzzMaster)
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val slave = LazyModule(new AXI4FuzzSlave)
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slave.node := master.node
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := master.module.io.finished
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}
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}
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class AXI4BridgeTest extends UnitTest(500000) {
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val dut = Module(LazyModule(new AXI4FuzzBridge).module)
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io.finished := dut.io.finished
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}
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