115 lines
4.3 KiB
Scala
115 lines
4.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import diplomacy._
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import regmapper._
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import scala.math.{min,max}
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class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends AXI4SlaveNode(AXI4SlavePortParameters(
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Seq(AXI4SlaveParameters(
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address = Seq(address),
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executable = executable,
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supportsWrite = TransferSizes(1, beatBytes),
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supportsRead = TransferSizes(1, beatBytes),
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interleavedId = Some(0))),
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beatBytes = beatBytes))
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{
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require (address.contiguous)
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// Calling this method causes the matching AXI4 bundle to be
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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val ar = bundleIn(0).ar
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val aw = bundleIn(0).aw
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val w = bundleIn(0).w
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val r = bundleIn(0).r
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val b = bundleIn(0).b
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val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, ar.bits.params.idBits)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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// Prefer to execute reads first
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in.valid := ar.valid || (aw.valid && w.valid)
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ar.ready := in.ready
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aw.ready := in.ready && !ar.valid && w .valid
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w .ready := in.ready && !ar.valid && aw.valid
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val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)
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val in_id = Mux(ar.valid, ar.bits.id, aw.bits.id)
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val mask = uncore.tilelink2.maskGen(ar.bits.addr, ar.bits.size, beatBytes)
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in.bits.read := ar.valid
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in.bits.index := addr >> log2Ceil(beatBytes)
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in.bits.data := w.bits.data
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in.bits.mask := Mux(ar.valid, mask, w.bits.strb)
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in.bits.extra := in_id
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// Invoke the register map builder and make it Irrevocable
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val out = Queue.irrevocable(
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RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
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entries = 1, flow = true)
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// No flow control needed
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out.ready := Mux(out.bits.read, r.ready, b.ready)
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r.valid := out.valid && out.bits.read
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b.valid := out.valid && !out.bits.read
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val out_id = if (r.bits.params.idBits == 0) UInt(0) else out.bits.extra
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r.bits.id := out_id
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r.bits.data := out.bits.data
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r.bits.last := Bool(true)
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r.bits.resp := AXI4Parameters.RESP_OKAY
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b.bits.id := out_id
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b.bits.resp := AXI4Parameters.RESP_OKAY
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}
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}
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object AXI4RegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a AXI4
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// register mapped device from a totally abstract register mapped device.
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abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule
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{
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val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
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val intnode = uncore.tilelink2.IntSourceNode(interrupts)
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}
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case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])
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class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
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{
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val interrupts = arg.interrupts
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val in = arg.in
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}
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class AXI4RegBundle[P](val params: P, arg: AXI4RegBundleArg) extends AXI4RegBundleBase(arg)
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class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: => B, router: AXI4RegisterRouterBase)
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extends LazyModuleImp(router) with HasRegMap
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{
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val io = bundleBuilder
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val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
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def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
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}
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class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp]
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(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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(bundleBuilder: AXI4RegBundleArg => B)
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(moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)
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extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
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{
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require (isPow2(size))
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// require (size >= 4096) ... not absolutely required, but highly recommended
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lazy val module = moduleBuilder(bundleBuilder(AXI4RegBundleArg(intnode.bundleOut, node.bundleIn)), this)
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}
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