38 lines
1.0 KiB
Scala
38 lines
1.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import chisel3.util.{Irrevocable, IrrevocableIO}
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object AXI4Parameters
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{
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// These are all fixed by the AXI4 standard:
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val lenBits = 8
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val sizeBits = 3
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val burstBits = 2
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val lockBits = 1
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val cacheBits = 4
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val protBits = 3
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val qosBits = 4
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val respBits = 2
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val CACHE_RALLOCATE = UInt(8, width = cacheBits)
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val CACHE_WALLOCATE = UInt(4, width = cacheBits)
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val CACHE_MODIFIABLE = UInt(2, width = cacheBits)
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val CACHE_BUFFERABLE = UInt(1, width = cacheBits)
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val PROT_PRIVILEDGED = UInt(1, width = protBits)
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val PROT_INSECURE = UInt(2, width = protBits)
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val PROT_INSTRUCTION = UInt(4, width = protBits)
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val BURST_FIXED = UInt(0, width = burstBits)
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val BURST_INCR = UInt(1, width = burstBits)
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val BURST_WRAP = UInt(2, width = burstBits)
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val RESP_OKAY = UInt(0, width = respBits)
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val RESP_EXOKAY = UInt(1, width = respBits)
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val RESP_SLVERR = UInt(2, width = respBits)
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val RESP_DECERR = UInt(3, width = respBits)
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}
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