116 lines
3.5 KiB
Scala
116 lines
3.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import diplomacy._
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import scala.math.max
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case class AXI4SlaveParameters(
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address: Seq[AddressSet],
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[BaseNode] = Seq(),
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supportsWrite: TransferSizes = TransferSizes.none,
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supportsRead: TransferSizes = TransferSizes.none,
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interleavedId: Option[Int] = None) // The device will not interleave read responses
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{
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address.foreach { a => require (a.finite) }
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val maxTransfer = max(supportsWrite.max, supportsRead.max)
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val maxAddress = address.map(_.max).max
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val minAlignment = address.map(_.alignment).min
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// The device had better not support a transfer larger than it's alignment
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require (minAlignment >= maxTransfer)
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}
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case class AXI4SlavePortParameters(
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slaves: Seq[AXI4SlaveParameters],
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beatBytes: Int)
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{
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require (!slaves.isEmpty)
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require (isPow2(beatBytes))
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val maxTransfer = slaves.map(_.maxTransfer).max
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val maxAddress = slaves.map(_.maxAddress).max
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// Check the link is not pointlessly wide
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require (maxTransfer >= beatBytes)
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// Check that the link can be implemented in AXI4
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require (maxTransfer <= beatBytes * (1 << AXI4Parameters.lenBits))
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Require disjoint ranges for addresses
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slaves.combinations(2).foreach { case Seq(x,y) =>
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x.address.foreach { a => y.address.foreach { b =>
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require (!a.overlaps(b))
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} }
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}
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}
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case class AXI4MasterParameters(
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id: IdRange = IdRange(0, 1),
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aligned: Boolean = false,
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class AXI4MasterPortParameters(
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masters: Seq[AXI4MasterParameters])
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{
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val endId = masters.map(_.id.end).max
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// Require disjoint ranges for ids
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masters.combinations(2).foreach { case Seq(x,y) => require (!x.id.overlaps(y.id)) }
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}
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case class AXI4BundleParameters(
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addrBits: Int,
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dataBits: Int,
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idBits: Int)
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{
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require (dataBits >= 8)
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require (addrBits >= 1)
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require (idBits >= 1)
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require (isPow2(dataBits))
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// Bring the globals into scope
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val lenBits = AXI4Parameters.lenBits
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val sizeBits = AXI4Parameters.sizeBits
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val burstBits = AXI4Parameters.burstBits
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val lockBits = AXI4Parameters.lockBits
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val cacheBits = AXI4Parameters.cacheBits
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val protBits = AXI4Parameters.protBits
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val qosBits = AXI4Parameters.qosBits
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val respBits = AXI4Parameters.respBits
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def union(x: AXI4BundleParameters) =
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AXI4BundleParameters(
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max(addrBits, x.addrBits),
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max(dataBits, x.dataBits),
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max(idBits, x.idBits))
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}
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object AXI4BundleParameters
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{
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def apply(master: AXI4MasterPortParameters, slave: AXI4SlavePortParameters) =
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new AXI4BundleParameters(
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addrBits = log2Up(slave.maxAddress+1),
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dataBits = slave.beatBytes * 8,
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idBits = log2Up(master.endId))
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}
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case class AXI4EdgeParameters(
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master: AXI4MasterPortParameters,
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slave: AXI4SlavePortParameters)
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{
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val bundle = AXI4BundleParameters(master, slave)
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}
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