59 lines
3.0 KiB
Scala
59 lines
3.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
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{
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def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
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def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
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def bundleO(eo: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, AXI4Bundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, AXI4Bundle(ei.map(_.bundle).reduce(_.union(_))))
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}
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def colour = "#00ccff" // bluish
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override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString
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override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString
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def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => { bi <> bo })
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}
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override def mixO(pd: AXI4MasterPortParameters, node: OutwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4MasterPortParameters =
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pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: AXI4SlavePortParameters, node: InwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4SlavePortParameters =
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pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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// Nodes implemented inside modules
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case class AXI4IdentityNode() extends IdentityNode(AXI4Imp)
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case class AXI4MasterNode(portParams: AXI4MasterPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(AXI4Imp)(portParams, numPorts)
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case class AXI4SlaveNode(portParams: AXI4SlavePortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(AXI4Imp)(portParams, numPorts)
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case class AXI4AdapterNode(
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masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters,
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slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 1,
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numSlavePorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(AXI4Imp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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// Nodes passed from an inner module
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case class AXI4OutputNode() extends OutputNode(AXI4Imp)
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case class AXI4InputNode() extends InputNode(AXI4Imp)
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// Nodes used for external ports
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case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
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case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
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case class AXI4InternalOutputNode(portParams: AXI4SlavePortParameters) extends InternalOutputNode(AXI4Imp)(portParams)
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case class AXI4InternalInputNode(portParams: AXI4MasterPortParameters) extends InternalInputNode(AXI4Imp)(portParams)
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