70 lines
3.0 KiB
Scala
70 lines
3.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.agents
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import Chisel._
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.devices._
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import config._
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/** The ManagerToClientStateless Bridge does not maintain any state for the messages
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* which pass through it. It simply passes the messages back and forth without any
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* tracking or translation.
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*
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* This can reduce area and timing in very constrained situations:
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* - The Manager and Client implement the same coherence protocol
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* - There are no probe or finish messages.
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* - The outer transaction ID is large enough to handle all possible inner
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* transaction IDs, such that no remapping state must be maintained.
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*
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* This bridge DOES NOT keep the uncached channel coherent with the cached
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* channel. Uncached requests to blocks cached by the L1 will not probe the L1.
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* As a result, uncached reads to cached blocks will get stale data until
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* the L1 performs a voluntary writeback, and uncached writes to cached blocks
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* will get lost, as the voluntary writeback from the L1 will overwrite the
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* changes. If your tile relies on probing the L1 data cache in order to
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* share data between the instruction cache and data cache (e.g. you are using
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* a non-blocking L1 D$) or if the tile has uncached channels capable of
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* writes (e.g. Hwacha and other RoCC accelerators), DO NOT USE THIS BRIDGE.
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*/
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class ManagerToClientStatelessBridge(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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val icid = io.inner.tlClientIdBits
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val ixid = io.inner.tlClientXactIdBits
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val oxid = io.outer.tlClientXactIdBits
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val innerCoh = io.inner.tlCoh.getClass
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val outerCoh = io.outer.tlCoh.getClass
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// Stateless Bridge is only usable in certain constrained situations.
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// Sanity check its usage here.
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require(io.inner.tlNCachingClients <= 1)
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require(icid + ixid <= oxid)
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require(innerCoh eq outerCoh,
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s"Coherence policies do not match: inner is ${innerCoh.getSimpleName}, outer is ${outerCoh.getSimpleName}")
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io.outer.acquire.valid := io.inner.acquire.valid
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io.inner.acquire.ready := io.outer.acquire.ready
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io.outer.acquire.bits := io.inner.acquire.bits
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io.outer.acquire.bits.client_xact_id := Cat(io.inner.acquire.bits.client_id, io.inner.acquire.bits.client_xact_id)
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io.outer.release.valid := io.inner.release.valid
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io.inner.release.ready := io.outer.release.ready
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io.outer.release.bits := io.inner.release.bits
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io.outer.release.bits.client_xact_id := Cat(io.inner.release.bits.client_id, io.inner.release.bits.client_xact_id)
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io.inner.grant.valid := io.outer.grant.valid
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io.outer.grant.ready := io.inner.grant.ready
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io.inner.grant.bits := io.outer.grant.bits
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io.inner.grant.bits.client_xact_id := io.outer.grant.bits.client_xact_id(ixid-1, 0)
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io.inner.grant.bits.client_id := io.outer.grant.bits.client_xact_id(icid+ixid-1, ixid)
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io.inner.probe.valid := Bool(false)
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io.inner.finish.ready := Bool(true)
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disconnectOuterProbeAndFinish()
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}
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