208 lines
7.2 KiB
Scala
208 lines
7.2 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package uncore.agents
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import Chisel._
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.util._
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import util._
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import config._
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class L2BroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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// Create TSHRs for outstanding transactions
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val irelTrackerList =
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(0 until nReleaseTransactors).map(id =>
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Module(new BufferedBroadcastVoluntaryReleaseTracker(id)))
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val iacqTrackerList =
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(nReleaseTransactors until nTransactors).map(id =>
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Module(new BufferedBroadcastAcquireTracker(id)))
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val trackerList = irelTrackerList ++ iacqTrackerList
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// Propagate incoherence flags
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trackerList.map(_.io.incoherent) foreach { _ := io.incoherent }
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// Create an arbiter for the one memory port
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val outerList = trackerList.map(_.io.outer)
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val outer_arb = Module(new ClientTileLinkIOArbiter(outerList.size)
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(p.alterPartial({ case TLId => p(OuterTLId) })))
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outer_arb.io.in <> outerList
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io.outer <> outer_arb.io.out
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// Handle acquire transaction initiation
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val irel_vs_iacq_conflict =
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io.inner.acquire.valid &&
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io.inner.release.valid &&
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io.irel().conflicts(io.iacq())
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doInputRoutingWithAllocation(
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in = io.inner.acquire,
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outs = trackerList.map(_.io.inner.acquire),
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allocs = trackerList.map(_.io.alloc.iacq),
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allocOverride = Some(!irel_vs_iacq_conflict))
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// Handle releases, which might be voluntary and might have data
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doInputRoutingWithAllocation(
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in = io.inner.release,
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outs = trackerList.map(_.io.inner.release),
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allocs = trackerList.map(_.io.alloc.irel))
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// Wire probe requests and grant reply to clients, finish acks from clients
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
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disconnectOuterProbeAndFinish()
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}
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class BroadcastXactTracker(implicit p: Parameters) extends XactTracker()(p) {
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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}
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trait BroadcastsToAllClients extends HasCoherenceAgentParameters {
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val coh = HierarchicalMetadata.onReset
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val inner_coh = coh.inner
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val outer_coh = coh.outer
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def full_representation = ~UInt(0, width = innerNCachingClients)
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}
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abstract class BroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
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extends VoluntaryReleaseTracker(trackerId)(p)
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with EmitsVoluntaryReleases
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with BroadcastsToAllClients {
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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// Checks for illegal behavior
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assert(!(state === s_idle && io.inner.release.fire() && io.alloc.irel.should && !io.irel().isVoluntary()),
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"VoluntaryReleaseTracker accepted Release that wasn't voluntary!")
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}
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abstract class BroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
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extends AcquireTracker(trackerId)(p)
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with EmitsVoluntaryReleases
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with BroadcastsToAllClients {
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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val alwaysWriteFullBeat = false
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val nSecondaryMisses = 1
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def iacq_can_merge = Bool(false)
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// Checks for illegal behavior
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// TODO: this could be allowed, but is a useful check against allocation gone wild
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assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq.should &&
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io.iacq().hasMultibeatData() && !io.iacq().first()),
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"AcquireTracker initialized with a tail data beat.")
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assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),
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"Broadcast Hub does not support Prefetches.")
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assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),
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"Broadcast Hub does not support PutAtomics.")
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}
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class BufferedBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
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extends BroadcastVoluntaryReleaseTracker(trackerId)(p)
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with HasDataBuffer {
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// Tell the parent if any incoming messages conflict with the ongoing transaction
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routeInParent(irelCanAlloc = Bool(true))
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// Start transaction by accepting inner release
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innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending)
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// A release beat can be accepted if we are idle, if its a mergeable transaction, or if its a tail beat
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io.inner.release.ready := state === s_idle || irel_can_merge || irel_same_xact
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when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data }
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// Dispatch outer release
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outerRelease(
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coh = outer_coh.onHit(M_XWR),
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data = data_buffer(vol_ognt_counter.up.idx),
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add_pending_send_bit = irel_is_allocating)
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quiesce() {}
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}
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class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
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extends BroadcastAcquireTracker(trackerId)(p)
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with HasByteWriteMaskBuffer {
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// Setup IOs used for routing in the parent
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routeInParent(iacqCanAlloc = Bool(true))
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// First, take care of accpeting new acquires or secondary misses
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// Handling of primary and secondary misses' data and write mask merging
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innerAcquire(
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can_alloc = Bool(false),
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next = s_inner_probe)
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io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact_multibeat
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// Track which clients yet need to be probed and make Probe message
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// If a writeback occurs, we can forward its data via the buffer,
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// and skip having to go outwards
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val skip_outer_acquire = pending_ignt_data.andR
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innerProbe(
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inner_coh.makeProbe(curr_probe_dst, xact_iacq, xact_addr_block),
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Mux(!skip_outer_acquire, s_outer_acquire, s_busy))
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// Handle incoming releases from clients, which may reduce sharer counts
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// and/or write back dirty data, and may be unexpected voluntary releases
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def irel_can_merge = io.irel().conflicts(xact_addr_block) &&
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io.irel().isVoluntary() &&
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!state.isOneOf(s_idle, s_meta_write) &&
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!all_pending_done &&
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!io.outer.grant.fire() &&
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!io.inner.grant.fire() &&
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!vol_ignt_counter.pending &&
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!blockInnerRelease()
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innerRelease(block_vol_ignt = vol_ognt_counter.pending)
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//TODO: accept vol irels when state === s_idle, operate like the VolRelTracker
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io.inner.release.ready := irel_can_merge || irel_same_xact
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mergeDataInner(io.inner.release)
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// If there was a writeback, forward it outwards
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outerRelease(
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block_orel = pending_put_data(vol_ognt_counter.up.idx),
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coh = outer_coh.onHit(M_XWR),
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data = data_buffer(vol_ognt_counter.up.idx))
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// Send outer request for miss
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outerAcquire(
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caching = !xact_iacq.isBuiltInType(),
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coh = outer_coh,
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data = data_buffer(ognt_counter.up.idx),
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wmask = wmask_buffer(ognt_counter.up.idx),
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next = s_busy)
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// Handle the response from outer memory
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mergeDataOuter(io.outer.grant)
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// Acknowledge or respond with data
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innerGrant(
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data = data_buffer(ignt_data_idx),
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external_pending = pending_orel || ognt_counter.pending || vol_ognt_counter.pending)
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when(iacq_is_allocating) {
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initializeProbes()
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}
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initDataInner(io.inner.acquire, iacq_is_allocating || iacq_is_merging)
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// Wait for everything to quiesce
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quiesce() { clearWmaskBuffer() }
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}
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