165 lines
6.4 KiB
Scala
165 lines
6.4 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package uncore.agents
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import Chisel._
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import config._
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import junctions.PAddrBits
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import uncore.tilelink._
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import uncore.converters._
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import uncore.coherence._
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import uncore.util._
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import util._
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case object NReleaseTransactors extends Field[Int]
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case object NProbeTransactors extends Field[Int]
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case object NAcquireTransactors extends Field[Int]
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trait HasCoherenceAgentParameters {
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implicit val p: Parameters
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val nReleaseTransactors = 1
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val nAcquireTransactors = p(NAcquireTransactors)
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val nTransactors = nReleaseTransactors + nAcquireTransactors
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val blockAddrBits = p(PAddrBits) - p(CacheBlockOffsetBits)
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val outerTLId = p(OuterTLId)
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val outerTLParams = p(TLKey(outerTLId))
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val outerDataBeats = outerTLParams.dataBeats
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val outerDataBits = outerTLParams.dataBitsPerBeat
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val outerBeatAddrBits = log2Up(outerDataBeats)
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val outerByteAddrBits = log2Up(outerDataBits/8)
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val outerWriteMaskBits = outerTLParams.writeMaskBits
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val innerTLId = p(InnerTLId)
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val innerTLParams = p(TLKey(innerTLId))
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val innerDataBeats = innerTLParams.dataBeats
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val innerDataBits = innerTLParams.dataBitsPerBeat
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val innerWriteMaskBits = innerTLParams.writeMaskBits
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val innerBeatAddrBits = log2Up(innerDataBeats)
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val innerByteAddrBits = log2Up(innerDataBits/8)
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val innerNCachingClients = innerTLParams.nCachingClients
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val maxManagerXacts = innerTLParams.maxManagerXacts
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require(outerDataBeats == innerDataBeats) //TODO: fix all xact_data Vecs to remove this requirement
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}
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abstract class CoherenceAgentModule(implicit val p: Parameters) extends Module
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with HasCoherenceAgentParameters
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abstract class CoherenceAgentBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCoherenceAgentParameters
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trait HasCoherenceAgentWiringHelpers {
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def doOutputArbitration[T <: TileLinkChannel](
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out: DecoupledIO[T],
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ins: Seq[DecoupledIO[T]]) {
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def lock(o: T) = o.hasMultibeatData()
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val arb = Module(new LockingRRArbiter(out.bits, ins.size, out.bits.tlDataBeats, Some(lock _)))
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out <> arb.io.out
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arb.io.in <> ins
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}
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def doInputRouting[T <: Bundle with HasManagerTransactionId](
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in: DecoupledIO[T],
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outs: Seq[DecoupledIO[T]]) {
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val idx = in.bits.manager_xact_id
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && idx === UInt(i) }
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in.ready := outs.map(_.ready).apply(idx)
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}
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/** Broadcasts valid messages on this channel to all trackers,
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* but includes logic to allocate a new tracker in the case where
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* no previously allocated tracker matches the new req's addr.
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*
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* When a match is reported, if ready is high the new transaction
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* is merged; when ready is low the transaction is being blocked.
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* When no match is reported, any high idles are presumed to be
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* from trackers that are available for allocation, and one is
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* assigned via alloc based on priority; if no idles are high then
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* all trackers are busy with other transactions. If idle is high
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* but ready is low, the tracker will be allocated but does not
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* have sufficient buffering for the data.
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*/
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def doInputRoutingWithAllocation[T <: TileLinkChannel with HasTileLinkData](
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in: DecoupledIO[T],
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outs: Seq[DecoupledIO[T]],
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allocs: Seq[TrackerAllocation],
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dataOverrides: Option[Seq[UInt]] = None,
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allocOverride: Option[Bool] = None,
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matchOverride: Option[Bool] = None) {
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val ready_bits = outs.map(_.ready).asUInt
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val can_alloc_bits = allocs.map(_.can).asUInt
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val should_alloc_bits = PriorityEncoderOH(can_alloc_bits)
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val match_bits = allocs.map(_.matches).asUInt
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val no_matches = !match_bits.orR
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val alloc_ok = allocOverride.getOrElse(Bool(true))
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val match_ok = matchOverride.getOrElse(Bool(true))
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in.ready := (Mux(no_matches, can_alloc_bits, match_bits) & ready_bits).orR && alloc_ok && match_ok
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outs.zip(allocs).zipWithIndex.foreach { case((out, alloc), i) =>
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out.valid := in.valid && match_ok && alloc_ok
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out.bits := in.bits
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dataOverrides foreach { d => out.bits.data := d(i) }
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alloc.should := should_alloc_bits(i) && no_matches && alloc_ok
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}
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}
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}
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trait HasInnerTLIO extends HasCoherenceAgentParameters {
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val inner = new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)}))
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val incoherent = Vec(inner.tlNCachingClients, Bool()).asInput
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def iacq(dummy: Int = 0) = inner.acquire.bits
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def iprb(dummy: Int = 0) = inner.probe.bits
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def irel(dummy: Int = 0) = inner.release.bits
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def ignt(dummy: Int = 0) = inner.grant.bits
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def ifin(dummy: Int = 0) = inner.finish.bits
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}
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trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters {
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val outer = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def ognt(dummy: Int = 0) = outer.grant.bits
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}
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trait HasCachedOuterTLIO extends HasCoherenceAgentParameters {
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val outer = new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)}))
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def oprb(dummy: Int = 0) = outer.probe.bits
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def orel(dummy: Int = 0) = outer.release.bits
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def ognt(dummy: Int = 0) = outer.grant.bits
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}
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class ManagerTLIO(implicit p: Parameters) extends CoherenceAgentBundle()(p)
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with HasInnerTLIO
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with HasUncachedOuterTLIO
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abstract class CoherenceAgent(implicit p: Parameters) extends CoherenceAgentModule()(p) {
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def innerTL: ManagerTileLinkIO
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def outerTL: ClientTileLinkIO
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def incoherent: Vec[Bool]
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}
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abstract class ManagerCoherenceAgent(implicit p: Parameters) extends CoherenceAgent()(p)
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with HasCoherenceAgentWiringHelpers {
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val io = new ManagerTLIO
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def innerTL = io.inner
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def outerTL = TileLinkIOWrapper(io.outer)
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def incoherent = io.incoherent
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}
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class HierarchicalTLIO(implicit p: Parameters) extends CoherenceAgentBundle()(p)
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with HasInnerTLIO
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with HasCachedOuterTLIO
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abstract class HierarchicalCoherenceAgent(implicit p: Parameters) extends CoherenceAgent()(p)
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with HasCoherenceAgentWiringHelpers {
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val io = new HierarchicalTLIO
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def innerTL = io.inner
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def outerTL = io.outer
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def incoherent = io.incoherent
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// TODO: Remove this function (and all its calls) when we support probing the L2
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def disconnectOuterProbeAndFinish() {
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io.outer.probe.ready := Bool(false)
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io.outer.finish.valid := Bool(false)
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assert(!io.outer.probe.valid, "L2 agent got illegal probe")
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}
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}
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