101 lines
3.0 KiB
Scala
101 lines
3.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import config._
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import junctions._
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import diplomacy._
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import uncore.devices._
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import rocket._
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import coreplex._
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import uncore.tilelink2._
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import util._
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import java.nio.file.{Files, Paths}
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import java.nio.{ByteBuffer, ByteOrder}
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class RangeManager {
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private var finalized = false
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private val l = collection.mutable.ListBuffer[(String, Int)]()
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def add(name: String, element: Int) = { require(!finalized); l += (name -> element) }
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def rangeMap = {
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finalized = true
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(l map {
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var sum = 0
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x => { sum += x._2; (x._1 -> (sum-x._2, sum)) }
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}).toMap
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}
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def range(name: String) = rangeMap(name)
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def print = {
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rangeMap.toSeq.sortBy(_._2).foreach { case (name, (start, end)) =>
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println(s"${name} on int ${start}-${end-1}")
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}
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}
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def sum = {
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finalized = true
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l.map(_._2).sum
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}
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}
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class ResourceManager[T] {
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private var finalized = false
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private val l = collection.mutable.ArrayBuffer[T]()
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def add(element: T) = { require(!finalized); l += element }
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def add(list: Seq[T]) = { require(!finalized); l ++= list }
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def get: Seq[T] = { finalized = true; l }
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}
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class GlobalVariable[T] {
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private var assigned = false
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private var variable: T = _
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def assign(value: T) = { require(!assigned); assigned = true; variable = value }
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def get: T = { require(assigned); variable }
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}
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object GenerateConfigString {
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def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
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val c = CoreplexParameters()(p)
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val res = new StringBuilder
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res append plic.globalConfigString
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res append clint.globalConfigString
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res append "core {\n"
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for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
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val isa = {
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val m = if (p(MulDivKey).nonEmpty) "m" else ""
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val a = if (p(UseAtomics)) "a" else ""
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val f = if (p(FPUKey).nonEmpty) "f" else ""
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val d = if (p(FPUKey).nonEmpty && p(XLen) > 32) "d" else ""
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val s = if (c.hasSupervisor) "s" else ""
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s"rv${p(XLen)}i$m$a$f$d$s"
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}
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append clint.hartConfigStrings(i)
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res append plic.hartConfigStrings(i)
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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peripheryManagers.foreach { manager => res append manager.dts }
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res append '\u0000'
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res.toString
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}
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}
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object GenerateBootROM {
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def apply(p: Parameters, address: BigInt, configString: String) = {
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val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
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val rom = ByteBuffer.wrap(romdata)
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rom.order(ByteOrder.LITTLE_ENDIAN)
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require(address == address.toInt)
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val configStringAddr = address.toInt + rom.capacity
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require(rom.getInt(12) == 0,
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"Config string address position should not be occupied by code")
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rom.putInt(12, configStringAddr)
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rom.array() ++ (configString.getBytes.toSeq)
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}
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}
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