104 lines
2.7 KiB
Scala
104 lines
2.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import coreplex._
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import uncore.axi4._
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class TestHarness(q: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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implicit val p = q
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val dut = Module(LazyModule(new ExampleRocketTop).module)
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for (int <- dut.io.interrupts(0))
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int := Bool(false)
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if (dut.io.mem_axi4.nonEmpty) {
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val memSize = p(ExtMem).size
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require(memSize % dut.io.mem_axi4.size == 0)
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for (axi4 <- dut.io.mem_axi4) {
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Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
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}
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}
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val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
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val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
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mmio_sim.io.axi4 <> dut.io.mmio_axi4
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val l2_axi4 = dut.io.l2_axi4(0)
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l2_axi4.ar.valid := Bool(false)
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l2_axi4.aw.valid := Bool(false)
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l2_axi4.w .valid := Bool(false)
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l2_axi4.r .ready := Bool(true)
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l2_axi4.b .ready := Bool(true)
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}
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class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
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val config = p(ExtMem)
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val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
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val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
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sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val axi4 = node.bundleIn
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}
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}
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}
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class SimDTM(implicit p: Parameters) extends BlackBox {
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val io = new Bundle {
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val clk = Clock(INPUT)
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val reset = Bool(INPUT)
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val debug = new uncore.devices.DebugBusIO
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val exit = UInt(OUTPUT, 32)
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}
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def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO, tbsuccess: Bool) = {
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io.clk := tbclk
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io.reset := tbreset
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dutio <> io.debug
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tbsuccess := io.exit === UInt(1)
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when (io.exit >= UInt(2)) {
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printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
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stop(1)
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}
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}
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}
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class JTAGVPI(implicit val p: Parameters) extends BlackBox {
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val io = new Bundle {
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val jtag = new JTAGIO(false)
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val enable = Bool(INPUT)
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val init_done = Bool(INPUT)
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}
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def connect(dutio: JTAGIO, tbreset: Bool, tbsuccess: Bool) = {
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dutio <> io.jtag
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// To be proper,
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// TRST should really be synchronized
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// with TCK. But this is a fairly
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// accurate representation of how
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// HW may drive this signal.
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// Neither OpenOCD nor JtagVPI drive TRST.
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dutio.TRST := tbreset
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io.enable := ~tbreset
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io.init_done := ~tbreset
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// Success is determined by the gdbserver
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// which is controlling this simulation.
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tbsuccess := Bool(false)
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}
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}
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