81 lines
2.5 KiB
Scala
81 lines
2.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import uncore.devices._
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import junctions._
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import util._
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import config._
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case object IncludeJtagDTM extends Field[Boolean]
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/* JTAG-based Debug Transport Module
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* and synchronization logic.
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*
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* This implements JTAG interface described
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* in the RISC-V Debug Specification
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*
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* This Module is currently a
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* wrapper around a JTAG implementation
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* of the Debug Transport Module.
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* This is black-boxed because
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* Chisel doesn't currently support:
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* - Negative Edge Clocking
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* - Asynchronous Resets
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* (The tristate requirements of JTAG are exported from the
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* Chisel domain with the DRV_TDO signal).
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*
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* The 'TRST' input is used to asynchronously
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* reset the Debug Transport Module and the
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* DTM side of the synchronizer.
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* This design requires that TRST be
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* synchronized to TCK (for de-assert) outside
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* of this module. Your top level code should ensure
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* that TRST is asserted before the rocket-chip core
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* comes out of reset.
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* Note that TRST is an optional
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* part of the JTAG protocol, but it is not
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* optional for interfacing with this logic.
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*
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*/
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class JtagDTMWithSync(implicit val p: Parameters) extends Module {
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// io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box
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val io = new Bundle {
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val jtag = new JTAGIO(true).flip
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val debug = new AsyncDebugBusIO
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}
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val req_width = io.debug.req.mem(0).getWidth
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val resp_width = io.debug.resp.mem(0).getWidth
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val jtag_dtm = Module(new DebugTransportModuleJtag(req_width, resp_width))
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jtag_dtm.io.jtag <> io.jtag
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val io_debug_bus = Wire (new DebugBusIO)
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io.debug <> ToAsyncDebugBus(io_debug_bus)
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val dtm_req = jtag_dtm.io.dtm_req
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val dtm_resp = jtag_dtm.io.dtm_resp
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// Translate from straight 'bits' interface of the blackboxes
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// into the Resp/Req data structures.
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io_debug_bus.req.valid := dtm_req.valid
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io_debug_bus.req.bits := new DebugBusReq(p(DMKey).nDebugBusAddrSize).fromBits(dtm_req.bits)
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dtm_req.ready := io_debug_bus.req.ready
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dtm_resp.valid := io_debug_bus.resp.valid
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dtm_resp.bits := io_debug_bus.resp.bits.asUInt
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io_debug_bus.resp.ready := dtm_resp.ready
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}
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class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {
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val io = new Bundle {
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val jtag = new JTAGIO(true).flip()
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val dtm_req = new DecoupledIO(UInt(width = reqSize))
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val dtm_resp = new DecoupledIO(UInt(width = respSize)).flip()
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}
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}
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