80 lines
2.0 KiB
Scala
80 lines
2.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import rocket._
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Boolean]
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abstract class BareTop(implicit val p: Parameters) extends LazyModule {
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TopModule.contents = Some(this)
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}
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle {
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val outer = _outer
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}
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abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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/** Base Top with no Periphery */
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trait TopNetwork extends HasPeripheryParameters {
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val module: TopNetworkModule
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TLImp.emitMonitors = p(TLEmitMonitors)
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// Add a SoC and peripheral bus
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val socBus = LazyModule(new TLXbar)
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val peripheryBus = LazyModule(new TLXbar)
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val intBus = LazyModule(new IntXbar)
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peripheryBus.node :=
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TLWidthWidget(socBusConfig.beatBytes)(
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TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
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socBus.node))
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}
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trait TopNetworkBundle extends HasPeripheryParameters {
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val outer: TopNetwork
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implicit val p = outer.p
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}
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trait TopNetworkModule extends HasPeripheryParameters {
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val io: TopNetworkBundle
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val outer: TopNetwork
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implicit val p = outer.p
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}
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/** Base Top with no Periphery */
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class BaseTop(implicit p: Parameters) extends BareTop
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with TopNetwork {
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override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
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}
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class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
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with TopNetworkBundle
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with TopNetworkModule
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trait L2Crossbar extends TopNetwork {
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val l2 = LazyModule(new TLXbar)
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}
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trait L2CrossbarBundle extends TopNetworkBundle {
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}
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trait L2CrossbarModule extends TopNetworkModule {
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}
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