226 lines
8.1 KiB
Scala
226 lines
8.1 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package rocket
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import Chisel._
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import util._
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import Chisel.ImplicitConversions._
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import scala.math._
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import config._
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import diplomacy._
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import uncore.util._
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import uncore.tilelink2._
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case object PgLevels extends Field[Int]
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case object ASIdBits extends Field[Int]
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trait HasTLBParameters extends HasCoreParameters {
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val entries = p(p(CacheName)).nTLBEntries
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val cacheBlockBytes = p(CacheBlockBytes)
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val camAddrBits = log2Ceil(entries)
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val camTagBits = asIdBits + vpnBits
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}
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class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
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val vpn = UInt(width = vpnBitsExtended)
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val passthrough = Bool()
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val instruction = Bool()
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val store = Bool()
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}
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class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
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// lookup responses
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val miss = Bool(OUTPUT)
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val ppn = UInt(OUTPUT, ppnBits)
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val xcpt_ld = Bool(OUTPUT)
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val xcpt_st = Bool(OUTPUT)
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val xcpt_if = Bool(OUTPUT)
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val cacheable = Bool(OUTPUT)
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}
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class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
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val io = new Bundle {
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val req = Decoupled(new TLBReq).flip
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val resp = new TLBResp
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val ptw = new TLBPTWIO
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}
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val valid = Reg(init = UInt(0, entries))
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val ppns = Reg(Vec(entries, UInt(width = ppnBits)))
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val tags = Reg(Vec(entries, UInt(width = asIdBits + vpnBits)))
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val r_refill_tag = Reg(UInt(width = asIdBits + vpnBits))
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val r_refill_waddr = Reg(UInt(width = log2Ceil(entries)))
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val r_req = Reg(new TLBReq)
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val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
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val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
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val priv_s = priv === PRV.S
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val priv_uses_vm = priv <= PRV.S && !io.ptw.status.debug
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// share a single physical memory attribute checker (unshare if critical path)
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val passthrough_ppn = io.req.bits.vpn(ppnBits-1, 0)
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val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
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val do_refill = Bool(usingVM) && io.ptw.resp.valid
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val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
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val mpu_physaddr = mpu_ppn << pgIdxBits
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val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
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def fastCheck(member: TLManagerParameters => Boolean) =
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legal_address && Mux1H(edge.manager.findFast(mpu_physaddr), edge.manager.managers.map(m => Bool(member(m))))
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val prot_r = fastCheck(_.supportsGet)
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val prot_w = fastCheck(_.supportsPutFull)
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val prot_x = fastCheck(_.executable)
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val cacheable = fastCheck(_.supportsAcquire)
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val allSizes = TransferSizes(1, cacheBlockBytes)
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val amoSizes = TransferSizes(1, xLen/8)
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edge.manager.managers.foreach { m =>
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require (m.minAlignment >= 4096, s"MemoryMap region ${m.name} must be page-aligned (is ${m.minAlignment})")
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require (!m.supportsGet || m.supportsGet .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
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require (!m.supportsPutFull || m.supportsPutFull.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
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require (!m.supportsAcquire || m.supportsAcquire.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquire} Acquire, but must support ${allSizes}")
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require (!m.supportsLogical || m.supportsLogical.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
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require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
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}
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val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
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val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
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val hitsVec = (0 until entries).map(i => valid(i) && vm_enabled && tags(i) === lookup_tag) :+ !vm_enabled
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val hits = hitsVec.asUInt
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// permission bit arrays
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val pte_array = Reg(new PTE)
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val u_array = Reg(UInt(width = entries)) // user permission
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val sw_array = Reg(UInt(width = entries)) // write permission
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val sx_array = Reg(UInt(width = entries)) // execute permission
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val sr_array = Reg(UInt(width = entries)) // read permission
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val xr_array = Reg(UInt(width = entries)) // read permission to executable page
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val cash_array = Reg(UInt(width = entries)) // cacheable
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val dirty_array = Reg(UInt(width = entries)) // PTE dirty bit
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when (do_refill) {
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val pte = io.ptw.resp.bits.pte
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ppns(r_refill_waddr) := pte.ppn
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tags(r_refill_waddr) := r_refill_tag
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val mask = UIntToOH(r_refill_waddr)
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valid := valid | mask
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u_array := Mux(pte.u, u_array | mask, u_array & ~mask)
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sw_array := Mux(pte.sw() && prot_w, sw_array | mask, sw_array & ~mask)
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sx_array := Mux(pte.sx() && prot_x, sx_array | mask, sx_array & ~mask)
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sr_array := Mux(pte.sr() && prot_r, sr_array | mask, sr_array & ~mask)
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xr_array := Mux(pte.sx() && prot_r, xr_array | mask, xr_array & ~mask)
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cash_array := Mux(cacheable, cash_array | mask, cash_array & ~mask)
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dirty_array := Mux(pte.d, dirty_array | mask, dirty_array & ~mask)
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}
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val plru = new PseudoLRU(entries)
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val repl_waddr = Mux(!valid.andR, PriorityEncoder(~valid), plru.replace)
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val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.pum, u_array, UInt(0)), u_array)
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val w_array = Cat(prot_w, priv_ok & sw_array)
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val x_array = Cat(prot_x, priv_ok & sx_array)
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val r_array = Cat(prot_r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
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val c_array = Cat(cacheable, cash_array)
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val bad_va =
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if (vpnBits == vpnBitsExtended) Bool(false)
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else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
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// it's only a store hit if the dirty bit is set
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val tlb_hits = hits(entries-1, 0) & (dirty_array | ~Mux(io.req.bits.store, w_array, UInt(0)))
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val tlb_hit = tlb_hits.orR
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val tlb_miss = vm_enabled && !bad_va && !tlb_hit
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when (io.req.valid && !tlb_miss) {
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plru.access(OHToUInt(hits(entries-1, 0)))
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}
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io.req.ready := state === s_ready
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io.resp.xcpt_ld := bad_va || (~r_array & hits).orR
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io.resp.xcpt_st := bad_va || (~w_array & hits).orR
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io.resp.xcpt_if := bad_va || (~x_array & hits).orR
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io.resp.cacheable := (c_array & hits).orR
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io.resp.miss := do_refill || tlb_miss
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io.resp.ppn := Mux1H(hitsVec, ppns :+ passthrough_ppn)
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io.ptw.req.valid := state === s_request
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io.ptw.req.bits <> io.ptw.status
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io.ptw.req.bits.addr := r_refill_tag
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io.ptw.req.bits.store := r_req.store
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io.ptw.req.bits.fetch := r_req.instruction
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if (usingVM) {
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when (io.req.fire() && tlb_miss) {
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state := s_request
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r_refill_tag := lookup_tag
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r_refill_waddr := repl_waddr
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r_req := io.req.bits
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}
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when (state === s_request) {
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when (io.ptw.invalidate) {
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state := s_ready
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}
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when (io.ptw.req.ready) {
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state := s_wait
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when (io.ptw.invalidate) { state := s_wait_invalidate }
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}
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}
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when (state === s_wait && io.ptw.invalidate) {
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state := s_wait_invalidate
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}
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when (io.ptw.resp.valid) {
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state := s_ready
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}
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when (io.ptw.invalidate) {
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valid := 0
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}
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}
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}
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class DecoupledTLB(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val req = Decoupled(new TLBReq).flip
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val resp = Decoupled(new TLBResp)
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val ptw = new TLBPTWIO
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}
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val req = Reg(new TLBReq)
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val resp = Reg(new TLBResp)
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val tlb = Module(new TLB)
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val s_idle :: s_tlb_req :: s_tlb_resp :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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when (io.req.fire()) {
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req := io.req.bits
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state := s_tlb_req
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}
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when (tlb.io.req.fire()) {
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state := s_tlb_resp
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}
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when (state === s_tlb_resp) {
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when (tlb.io.resp.miss) {
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state := s_tlb_req
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} .otherwise {
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resp := tlb.io.resp
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state := s_done
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}
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}
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when (io.resp.fire()) { state := s_idle }
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io.req.ready := state === s_idle
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tlb.io.req.valid := state === s_tlb_req
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tlb.io.req.bits := req
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io.resp.valid := state === s_done
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io.resp.bits := resp
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io.ptw <> tlb.io.ptw
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}
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