139 lines
5.1 KiB
Scala
139 lines
5.1 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import uncore.tilelink._
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import util._
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import Chisel.ImplicitConversions._
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import config._
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class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended)
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val speculative = Bool()
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = Valid(new BTBResp)
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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val xcpt_if = Bool()
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val replay = Bool()
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}
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class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val flush_icache = Bool(OUTPUT)
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val flush_tlb = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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}
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class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
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val io = new Bundle {
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val cpu = new FrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = new ClientUncachedTileLinkIO
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val resetVector = UInt(INPUT, vaddrBitsExtended)
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}
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val icache = Module(new ICache(latency = 2))
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val tlb = Module(new TLB)
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val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))
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val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
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val s1_speculative = Reg(Bool())
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=io.resetVector)
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_xcpt_if = Reg(init=Bool(false))
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val s2_speculative = Reg(init=Bool(false))
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val s2_cacheable = Reg(init=Bool(false))
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val ntpc = ~(~s1_pc | (coreInstBytes*fetchWidth-1)) + UInt(coreInstBytes*fetchWidth)
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val ntpc_same_block = (ntpc & rowBytes) === (s1_pc & rowBytes)
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val predicted_npc = Wire(init = ntpc)
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val predicted_taken = Wire(init = Bool(false))
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val icmiss = s2_valid && !icache.io.resp.valid
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val npc = Mux(icmiss, s2_pc, predicted_npc)
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val s0_same_block = !predicted_taken && !icmiss && !io.cpu.req.valid && ntpc_same_block
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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s1_same_block := s0_same_block && !tlb.io.resp.miss
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s1_pc_ := io.cpu.npc
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// consider RVC fetches across blocks to be non-speculative if the first
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// part was non-speculative
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val s0_speculative =
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if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken
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else Bool(true)
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s1_speculative := Mux(icmiss, s2_speculative, s0_speculative)
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s2_valid := !icmiss
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when (!icmiss) {
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s2_pc := s1_pc
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s2_speculative := s1_speculative
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s2_cacheable := tlb.io.resp.cacheable
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s2_xcpt_if := tlb.io.resp.xcpt_if && !tlb.io.resp.miss
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}
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}
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when (io.cpu.req.valid) {
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s1_same_block := Bool(false)
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s1_pc_ := io.cpu.npc
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s1_speculative := io.cpu.req.bits.speculative
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s2_valid := Bool(false)
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}
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if (p(BtbKey).nEntries > 0) {
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val btb = Module(new BTB)
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc_
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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when (!stall && !icmiss) {
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btb.io.req.valid := true
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s2_btb_resp_valid := btb.io.resp.valid
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s2_btb_resp_bits := btb.io.resp.bits
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}
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when (btb.io.resp.valid && btb.io.resp.bits.taken) {
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predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
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predicted_taken := Bool(true)
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}
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}
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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tlb.io.req.bits.store := Bool(false)
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io.mem <> icache.io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.addr := io.cpu.npc
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_ppn := tlb.io.resp.ppn
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
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icache.io.s2_kill := s2_speculative && !s2_cacheable
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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require(fetchWidth * coreInstBytes <= rowBytes && isPow2(fetchWidth))
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc.extract(log2Ceil(rowBytes)-1,log2Ceil(fetchWidth*coreInstBytes)) << log2Ceil(fetchWidth*coreInstBits))
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io.cpu.resp.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.resp.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt_if
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io.cpu.resp.bits.btb.valid := s2_btb_resp_valid
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io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
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}
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