115 lines
3.4 KiB
Scala
115 lines
3.4 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import config._
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import util.{ParameterizedBundle, DecoupledHelper}
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class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
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{
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val io = new Bundle {
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val requestor = Vec(n, new HellaCacheIO).flip
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val mem = new HellaCacheIO
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}
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if (n == 1) {
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io.mem <> io.requestor.head
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} else {
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val s1_id = Reg(UInt())
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val s2_id = Reg(next=s1_id)
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io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
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io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
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io.requestor(0).req.ready := io.mem.req.ready
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for (i <- 1 until n)
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io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
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for (i <- n-1 to 0 by -1) {
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val req = io.requestor(i).req
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def connect_s0() = {
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io.mem.req.bits.cmd := req.bits.cmd
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io.mem.req.bits.typ := req.bits.typ
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io.mem.req.bits.addr := req.bits.addr
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io.mem.req.bits.phys := req.bits.phys
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io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n)))
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s1_id := UInt(i)
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}
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def connect_s1() = {
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io.mem.s1_kill := io.requestor(i).s1_kill
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io.mem.s1_data := io.requestor(i).s1_data
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}
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if (i == n-1) {
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connect_s0()
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connect_s1()
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} else {
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when (req.valid) { connect_s0() }
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when (s1_id === UInt(i)) { connect_s1() }
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}
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}
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for (i <- 0 until n) {
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val resp = io.requestor(i).resp
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
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resp.valid := io.mem.resp.valid && tag_hit
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io.requestor(i).xcpt := io.mem.xcpt
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io.requestor(i).ordered := io.mem.ordered
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io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
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resp.bits := io.mem.resp.bits
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resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
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io.requestor(i).replay_next := io.mem.replay_next
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}
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}
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}
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class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)
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(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val in_req = Vec(n, Decoupled(reqTyp)).flip
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val in_resp = Vec(n, Decoupled(respTyp))
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val out_req = Decoupled(reqTyp)
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val out_resp = Decoupled(respTyp).flip
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}
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if (n > 1) {
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val route_q = Module(new Queue(UInt(width = log2Up(n)), 2))
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val req_arb = Module(new RRArbiter(reqTyp, n))
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req_arb.io.in <> io.in_req
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val req_helper = DecoupledHelper(
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req_arb.io.out.valid,
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route_q.io.enq.ready,
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io.out_req.ready)
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io.out_req.bits := req_arb.io.out.bits
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io.out_req.valid := req_helper.fire(io.out_req.ready)
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route_q.io.enq.bits := req_arb.io.chosen
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route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready)
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req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid)
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val resp_sel = route_q.io.deq.bits
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val resp_ready = io.in_resp(resp_sel).ready
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val resp_helper = DecoupledHelper(
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resp_ready,
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route_q.io.deq.valid,
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io.out_resp.valid)
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val resp_valid = resp_helper.fire(resp_ready)
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for (i <- 0 until n) {
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io.in_resp(i).bits := io.out_resp.bits
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io.in_resp(i).valid := resp_valid && resp_sel === UInt(i)
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}
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route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid)
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io.out_resp.ready := resp_helper.fire(io.out_resp.valid)
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} else {
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io.out_req <> io.in_req.head
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io.in_resp.head <> io.out_resp
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}
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}
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