104 lines
4.2 KiB
Scala
104 lines
4.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import diplomacy._
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import config._
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import uncore.constants._
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import uncore.tilelink2._
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import uncore.util._
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class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule {
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val coreDataBytes = p(XLen)/8
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val node = TLManagerNode(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsArithmetic = if (p(UseAtomics)) TransferSizes(1, coreDataBytes) else TransferSizes.none,
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supportsLogical = if (p(UseAtomics)) TransferSizes(1, coreDataBytes) else TransferSizes.none,
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supportsPutPartial = TransferSizes(1, coreDataBytes),
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supportsPutFull = TransferSizes(1, coreDataBytes),
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supportsGet = TransferSizes(1, coreDataBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = coreDataBytes,
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minLatency = 1))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val tl_in = node.bundleIn
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val dmem = new HellaCacheIO
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}
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val tl_in = io.tl_in(0)
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val edge = node.edgesIn(0)
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val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
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val state = Reg(init = s_ready)
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when (io.dmem.resp.valid) { state := s_grant }
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when (tl_in.d.fire()) { state := s_ready }
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when (io.dmem.s2_nack) { state := s_replay }
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when (io.dmem.req.fire()) { state := s_wait }
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val acq = Reg(tl_in.a.bits)
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when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data }
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when (tl_in.a.fire()) { acq := tl_in.a.bits }
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val isWrite = acq.opcode === TLMessages.PutFullData || acq.opcode === TLMessages.PutPartialData
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val isRead = !edge.hasData(acq)
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def formCacheReq(acq: TLBundleA) = {
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val req = Wire(new HellaCacheReq)
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req.cmd := MuxLookup(acq.opcode, Wire(M_XRD), Array(
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TLMessages.PutFullData -> M_XWR,
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TLMessages.PutPartialData -> M_XWR,
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TLMessages.ArithmeticData -> MuxLookup(acq.param, Wire(M_XRD), Array(
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TLAtomics.MIN -> M_XA_MIN,
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TLAtomics.MAX -> M_XA_MAX,
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TLAtomics.MINU -> M_XA_MINU,
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TLAtomics.MAXU -> M_XA_MAXU,
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TLAtomics.ADD -> M_XA_ADD)),
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TLMessages.LogicalData -> MuxLookup(acq.param, Wire(M_XRD), Array(
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TLAtomics.XOR -> M_XA_XOR,
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TLAtomics.OR -> M_XA_OR,
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TLAtomics.AND -> M_XA_AND,
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TLAtomics.SWAP -> M_XA_SWAP)),
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TLMessages.Get -> M_XRD))
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// treat all loads as full words, so bytes appear in correct lane
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req.typ := Mux(isRead, log2Ceil(coreDataBytes), acq.size)
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req.addr := Mux(isRead, ~(~acq.address | (coreDataBytes-1)), acq.address)
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req.tag := UInt(0)
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req
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}
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val ready = state === s_ready || tl_in.d.fire()
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io.dmem.req.valid := (tl_in.a.valid && ready) || state === s_replay
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tl_in.a.ready := io.dmem.req.ready && ready
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io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))
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// the TL data is already in the correct byte lane, but the D$
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// expects right-justified store data, so that it can steer the bytes.
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io.dmem.s1_data := new LoadGen(acq.size, Bool(false), acq.address(log2Ceil(coreDataBytes)-1,0), acq.data, Bool(false), coreDataBytes).data
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io.dmem.s1_kill := false
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io.dmem.invalidate_lr := false
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// place AMO data in correct word lane
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val minAMOBytes = 4
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val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
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val alignedGrantData = Mux(acq.size <= log2Ceil(minAMOBytes), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
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tl_in.d.valid := io.dmem.resp.valid || state === s_grant
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tl_in.d.bits := Mux(isWrite,
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edge.AccessAck(acq, UInt(0)),
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edge.AccessAck(acq, UInt(0), UInt(0)))
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tl_in.d.bits.data := alignedGrantData
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// Tie off unused channels
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tl_in.b.valid := Bool(false)
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tl_in.c.ready := Bool(true)
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tl_in.e.ready := Bool(true)
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}
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}
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