229 lines
7.8 KiB
Scala
229 lines
7.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package regmapper
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import Chisel._
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import chisel3.util.{Irrevocable}
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import util.{AsyncQueue,AsyncResetRegVec}
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// A very simple flow control state machine, run in the specified clock domain
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class BusyRegisterCrossing extends Module {
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val io = new Bundle {
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val bypass = Bool(INPUT)
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val master_request_valid = Bool(INPUT)
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val master_request_ready = Bool(OUTPUT)
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val master_response_valid = Bool(OUTPUT)
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val master_response_ready = Bool(INPUT)
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val crossing_request_valid = Bool(OUTPUT)
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val crossing_request_ready = Bool(INPUT)
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// ... no crossing_response_ready; we are always ready
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}
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val busy = RegInit(Bool(false))
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val bypass = Reg(Bool())
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when (io.crossing_request_ready || Mux(busy, bypass, io.bypass)) {
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busy := Mux(busy, !io.master_response_ready, io.master_request_valid)
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}
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when (io.master_request_valid && io.master_request_ready) {
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bypass := io.bypass
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}
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io.crossing_request_valid := io.master_request_valid && !io.bypass && !busy
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io.master_request_ready := (io.bypass || io.crossing_request_ready) && !busy
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io.master_response_valid := (bypass || io.crossing_request_ready) && busy
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}
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class RegisterCrossingAssertion extends Module {
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val io = new Bundle {
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val master_bypass = Bool(INPUT)
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val slave_reset = Bool(INPUT)
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}
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val up = RegInit(Bool(false))
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up := !io.slave_reset
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assert (io.master_bypass || !up || !io.slave_reset)
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}
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// RegField should support connecting to one of these
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class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
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val request = Decoupled(gen).flip
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val response = Irrevocable(Bool()) // ignore .bits
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}
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// To turn off=>on a domain:
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// A. To turn disable the master domain
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// 1. wait for all inflight traffic to resolve
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// 2. assert master reset
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// 3. (optional) stop the master clock
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// --- YOU MAY NOT TURN OFF POWER ---
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// 4. re-enable the clock
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// 5. deassert reset
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// B. To turn off the slave domain
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// 1. assert bypass
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// 2. wait for inflight traffic to resolve
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// 3. assert slave reset
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// 4. (optional) stop the slave clock
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// --- YOU MAY NOT TURN OFF POWER ---
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// 5. re-enable the clock
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// 6. deassert reset
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// 7. deassert bypass
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//
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// If you need to cut power, use something that support isolation gates.
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class RegisterWriteCrossingIO[T <: Data](gen: T) extends Bundle {
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// Master clock domain
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val master_clock = Clock(INPUT)
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val master_reset = Bool(INPUT)
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val master_port = new RegisterWriteIO(gen)
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// Bypass requests from the master to be noops
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val master_bypass = Bool(INPUT)
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// Slave clock domain
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val slave_clock = Clock(INPUT)
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val slave_reset = Bool(INPUT)
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val slave_register = gen.asOutput
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val slave_valid = Bool(OUTPUT) // is high on 1st cycle slave_register has a new value
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}
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class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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val io = new RegisterWriteCrossingIO(gen)
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// The crossing must only allow one item inflight at a time
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val control = Module(new BusyRegisterCrossing)
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val crossing = Module(new AsyncQueue(gen, 1, sync, safe=false))
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control.clock := io.master_clock
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control.reset := io.master_reset
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crossing.io.enq_clock := io.master_clock
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crossing.io.enq_reset := io.master_reset
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crossing.io.deq_clock := io.slave_clock
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crossing.io.deq_reset := io.slave_reset
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control.io.bypass := io.master_bypass
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control.io.master_request_valid := io.master_port.request.valid
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control.io.master_response_ready := io.master_port.response.ready
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io.master_port.request.ready := control.io.master_request_ready
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io.master_port.response.valid := control.io.master_response_valid
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control.io.crossing_request_ready := crossing.io.enq.ready
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crossing.io.enq.valid := control.io.crossing_request_valid
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crossing.io.enq.bits := io.master_port.request.bits
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crossing.io.deq.ready := Bool(true)
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io.slave_valid := crossing.io.deq.valid
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io.slave_register := crossing.io.deq.bits
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val assertion = Module(new RegisterCrossingAssertion)
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assertion.clock := io.master_clock
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assertion.reset := io.master_reset
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assertion.io.master_bypass := io.master_bypass
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assertion.io.slave_reset := io.slave_reset
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}
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// RegField should support connecting to one of these
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class RegisterReadIO[T <: Data](gen: T) extends Bundle {
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val request = Decoupled(Bool()).flip // ignore .bits
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val response = Irrevocable(gen)
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}
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class RegisterReadCrossingIO[T <: Data](gen: T) extends Bundle {
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// Master clock domain
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val master_clock = Clock(INPUT)
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val master_reset = Bool(INPUT)
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val master_port = new RegisterReadIO(gen)
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// Bypass requests from the master to be noops
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val master_bypass = Bool(INPUT)
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// Slave clock domain
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val slave_clock = Clock(INPUT)
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val slave_reset = Bool(INPUT)
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val slave_register = gen.asInput
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}
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class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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val io = new RegisterReadCrossingIO(gen)
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// The crossing must only allow one item inflight at a time
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val control = Module(new BusyRegisterCrossing)
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val crossing = Module(new AsyncQueue(gen, 1, sync, safe=false))
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control.clock := io.master_clock
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control.reset := io.master_reset
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crossing.io.deq_clock := io.master_clock
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crossing.io.deq_reset := io.master_reset
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crossing.io.enq_clock := io.slave_clock
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crossing.io.enq_reset := io.slave_reset
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control.io.bypass := io.master_bypass
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control.io.master_request_valid := io.master_port.request.valid
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control.io.master_response_ready := io.master_port.response.ready
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io.master_port.request.ready := control.io.master_request_ready
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io.master_port.response.valid := control.io.master_response_valid
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control.io.crossing_request_ready := crossing.io.deq.valid
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crossing.io.deq.ready := control.io.crossing_request_valid
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io.master_port.response.bits := crossing.io.deq.bits
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crossing.io.enq.valid := Bool(true)
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crossing.io.enq.bits := io.slave_register
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val assertion = Module(new RegisterCrossingAssertion)
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assertion.clock := io.master_clock
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assertion.reset := io.master_reset
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assertion.io.master_bypass := io.master_bypass
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assertion.io.slave_reset := io.slave_reset
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}
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/** Wrapper to create an
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* asynchronously reset slave register which can be
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* both read and written
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* using crossing FIFOs.
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* The reset and allow assertion & de-assertion
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* should be synchronous to their respective
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* domains.
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*/
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object AsyncRWSlaveRegField {
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def apply(
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master_clock: Clock,
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master_reset: Bool,
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slave_clock: Clock,
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slave_reset: Bool,
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width: Int,
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init: Int,
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name: Option[String] = None,
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master_bypass: Bool = Bool(true)
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): (UInt, RegField) = {
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val async_slave_reg = Module(new AsyncResetRegVec(width, init))
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name.foreach(async_slave_reg.suggestName(_))
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async_slave_reg.reset := slave_reset
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async_slave_reg.clock := slave_clock
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val wr_crossing = Module (new RegisterWriteCrossing(UInt(width = width)))
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name.foreach(n => wr_crossing.suggestName(s"${n}_wcrossing"))
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wr_crossing.io.master_clock := master_clock
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wr_crossing.io.master_reset := master_reset
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wr_crossing.io.master_bypass := master_bypass
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wr_crossing.io.slave_clock := slave_clock
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wr_crossing.io.slave_reset := slave_reset
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async_slave_reg.io.en := wr_crossing.io.slave_valid
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async_slave_reg.io.d := wr_crossing.io.slave_register
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val rd_crossing = Module (new RegisterReadCrossing(UInt(width = width )))
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name.foreach(n => rd_crossing.suggestName(s"${n}_rcrossing"))
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rd_crossing.io.master_clock := master_clock
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rd_crossing.io.master_reset := master_reset
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rd_crossing.io.master_bypass := master_bypass
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rd_crossing.io.slave_clock := slave_clock
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rd_crossing.io.slave_reset := slave_reset
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rd_crossing.io.slave_register := async_slave_reg.io.q
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(async_slave_reg.io.q, RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port))
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}
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}
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