17 lines
405 B
Scala
17 lines
405 B
Scala
// See LICENSE.SiFive for license details.
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package junctions
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import Chisel._
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import config._
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class JTAGIO(drvTdo: Boolean = false) extends Bundle {
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val TCK = Clock(OUTPUT)
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val TMS = Bool(OUTPUT)
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val TDI = Bool(OUTPUT)
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val TDO = Bool(INPUT)
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val TRST = Bool(OUTPUT)
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val DRV_TDO = if (drvTdo) Some(Bool(INPUT)) else None
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override def cloneType = new JTAGIO(drvTdo).asInstanceOf[this.type]
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}
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