80 lines
2.7 KiB
Scala
80 lines
2.7 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package junctions
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import Chisel._
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import config._
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class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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val dataBytes = dataWidth / 8
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val nastiDataBytes = nastiXDataBits / 8
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val (write_cnt, write_done) = Counter(io.nasti.w.fire(), burstLen)
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val (read_cnt, read_done) = Counter(io.nasti.r.fire(), burstLen)
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val (req_cnt, reqs_done) = Counter(read_done, nBursts)
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val req_addr = Cat(req_cnt, UInt(0, log2Up(burstLen * dataBytes)))
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val write_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, write_cnt)
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val expected_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, read_cnt)
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val (s_idle :: s_write_addr :: s_write_data :: s_write_stall :: s_write_resp ::
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s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9)
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val state = Reg(init = s_idle)
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val (stall_cnt, stall_done) = Counter(state === s_read_stall, 2)
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Cat(write_data, write_data),
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last = (write_cnt === UInt(burstLen - 1)))
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.r.ready := (state === s_read_data)
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io.finished := (state === s_done)
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_stall }
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when (state === s_write_stall) { state := s_write_data }
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when (write_done) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_data }
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when (io.nasti.r.fire()) { state := s_read_stall }
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when (stall_done) { state := s_read_data }
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when (read_done) { state := s_write_addr }
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when (reqs_done) { state := s_done }
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val full_addr = req_addr + (read_cnt << UInt(log2Up(dataBytes)))
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val byteshift = full_addr(log2Up(nastiDataBytes) - 1, 0)
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val bitshift = Cat(byteshift, UInt(0, 3))
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val read_data = (io.nasti.r.bits.data >> bitshift) & Fill(dataWidth, UInt(1, 1))
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assert(!io.nasti.r.valid || read_data === expected_data,
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s"NastiDriver got wrong data")
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}
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