55 lines
1.9 KiB
Scala
55 lines
1.9 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package groundtest
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import Chisel._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.util._
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import util._
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import config._
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class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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with HasTileLinkParameters {
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val l2Config = p(CacheName("L2"))
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val capacityKb = l2Config.nSets * l2Config.nWays * l2Config.rowBits / (1024*8)
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val nblocks = capacityKb * 1024 / p(CacheBlockBytes)
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val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val active = state.isOneOf(s_prefetch, s_retrieve)
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val xact_pending = Reg(init = UInt(0, tlMaxClientXacts))
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val xact_id = PriorityEncoder(~xact_pending)
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val (req_block, round_done) = Counter(io.mem.head.acquire.fire(), nblocks)
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io.mem.head.acquire.valid := active && !xact_pending.andR
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io.mem.head.acquire.bits := Mux(state === s_prefetch,
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GetPrefetch(xact_id, UInt(memStartBlock) + req_block),
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GetBlock(xact_id, UInt(memStartBlock) + req_block))
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io.mem.head.grant.ready := xact_pending.orR
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def add_pending(acq: DecoupledIO[Acquire]): UInt =
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Mux(acq.fire(), UIntToOH(acq.bits.client_xact_id), UInt(0))
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def remove_pending(gnt: DecoupledIO[Grant]): UInt = {
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val last_grant = !gnt.bits.hasMultibeatData() ||
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gnt.bits.addr_beat === UInt(tlDataBeats - 1)
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~Mux(gnt.fire() && last_grant, UIntToOH(gnt.bits.client_xact_id), UInt(0))
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}
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xact_pending := (xact_pending |
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add_pending(io.mem.head.acquire)) &
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remove_pending(io.mem.head.grant)
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when (state === s_start) { state := s_prefetch }
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when (state === s_prefetch && round_done) { state := s_retrieve }
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when (state === s_retrieve && round_done) { state := s_finished }
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io.status.finished := (state === s_finished)
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io.status.timeout.valid := Bool(false)
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io.status.error.valid := Bool(false)
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}
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