117 lines
3.9 KiB
Scala
117 lines
3.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package groundtest
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import Chisel._
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import uncore.tilelink._
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import uncore.agents._
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import uncore.coherence.{InnerTLId, OuterTLId}
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import util._
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import rocketchip._
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import config._
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/**
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* An example bus mastering devices that writes some preset data to memory.
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* When it receives an MMIO put request, it starts writing out the data.
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* When it receives an MMIO get request, it responds with the progress of
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* the write. A grant data of 1 means it is still writing, grant data 0
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* means it has finished.
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*/
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class ExampleBusMaster(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
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val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
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val memStart = p(ExtMem).base
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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val io = new Bundle {
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val mmio = new ClientUncachedTileLinkIO()(mmioParams).flip
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val mem = new ClientUncachedTileLinkIO()(memParams)
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}
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val s_idle :: s_put :: s_resp :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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val send_resp = Reg(init = Bool(false))
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val r_acq = Reg(new AcquireMetadata)
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io.mmio.acquire.ready := !send_resp
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io.mmio.grant.valid := send_resp
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io.mmio.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = r_acq.getBuiltInGrantType(),
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client_xact_id = r_acq.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = r_acq.addr_beat,
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data = Mux(state === s_idle, UInt(0), UInt(1)))
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when (io.mmio.acquire.fire()) {
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send_resp := Bool(true)
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r_acq := io.mmio.acquire.bits
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when (state === s_idle && io.mmio.acquire.bits.hasData()) { state := s_put }
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}
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when (io.mmio.grant.fire()) { send_resp := Bool(false) }
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val (put_beat, put_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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when (put_done) { state := s_resp }
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when (io.mem.grant.fire()) { state := s_idle }
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io.mem.acquire.valid := state === s_put
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io.mem.acquire.bits := PutBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(memStartBlock),
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addr_beat = put_beat,
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data = put_beat)
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io.mem.grant.ready := state === s_resp
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}
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class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasTileLinkParameters {
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val (s_idle :: s_req_start :: s_resp_start :: s_req_poll :: s_resp_poll ::
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s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
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val state = Reg(init = s_idle)
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val busMasterBlock = p(ExtBus).base >> p(CacheBlockOffsetBits)
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val start_acq = Put(
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client_xact_id = UInt(0),
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addr_block = UInt(busMasterBlock),
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addr_beat = UInt(0),
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data = UInt(1))
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val poll_acq = Get(
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client_xact_id = UInt(0),
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addr_block = UInt(busMasterBlock),
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addr_beat = UInt(0))
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val check_acq = GetBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(memStartBlock))
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val acq = io.mem.head.acquire
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val gnt = io.mem.head.grant
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acq.valid := state.isOneOf(s_req_start, s_req_poll, s_req_check)
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acq.bits := MuxLookup(state, check_acq, Seq(
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s_req_start -> start_acq,
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s_req_poll -> poll_acq))
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gnt.ready := state.isOneOf(s_resp_start, s_resp_poll, s_resp_check)
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val (get_beat, get_done) = Counter(
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state === s_resp_check && gnt.valid, tlDataBeats)
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when (state === s_idle) { state := s_req_start }
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when (state === s_req_start && acq.ready) { state := s_resp_start }
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when (state === s_resp_start && gnt.valid) { state := s_req_poll }
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when (state === s_req_poll && acq.ready) { state := s_resp_poll }
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when (state === s_resp_poll && gnt.valid) {
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when (gnt.bits.data === UInt(0)) {
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state := s_req_check
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} .otherwise { state := s_req_poll }
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}
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when (state === s_req_check && acq.ready) { state := s_resp_check }
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when (get_done) { state := s_done }
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io.status.finished := state === s_done
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assert(state =/= s_resp_check || !gnt.valid ||
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gnt.bits.data === get_beat,
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"BusMasterTest: data does not match")
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}
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