261 lines
11 KiB
Scala
261 lines
11 KiB
Scala
// See LICENSE.SiFive for license details.
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package diplomacy
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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// DI = Downwards flowing Parameters received on the inner side of the node
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// UI = Upwards flowing Parameters generated by the inner side of the node
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// EI = Edge Parameters describing a connection on the inner side of the node
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// BI = Bundle type used when connecting to the inner side of the node
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trait InwardNodeImp[DI, UI, EI, BI <: Data]
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{
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def edgeI(pd: DI, pu: UI): EI
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def bundleI(ei: Seq[EI]): Vec[BI]
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def colour: String
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def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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// optional methods to track node graph
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def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu // insert node into parameters
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def getO(pu: UI): Option[BaseNode] = None // most-outward common node
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def labelI(ei: EI) = ""
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}
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// DO = Downwards flowing Parameters generated by the outer side of the node
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// UO = Upwards flowing Parameters received on the outer side of the node
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// EO = Edge Parameters describing a connection on the outer side of the node
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// BO = Bundle type used when connecting to the outer side of the node
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trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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{
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def edgeO(pd: DO, pu: UO): EO
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def bundleO(eo: Seq[EO]): Vec[BO]
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// optional methods to track node graph
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def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd // insert node into parameters
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def getI(pd: DO): Option[BaseNode] = None // most-inward common node
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def labelO(eo: EO) = ""
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}
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class BaseNode
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{
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// You cannot create a Node outside a LazyModule!
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require (!LazyModule.stack.isEmpty)
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val lazyModule = LazyModule.stack.head
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val index = lazyModule.nodes.size
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lazyModule.nodes = this :: lazyModule.nodes
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def nodename = getClass.getName.split('.').last
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def name = lazyModule.name + "." + nodename
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def omitGraphML = outputs.isEmpty && inputs.isEmpty
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protected[diplomacy] def gci: Option[BaseNode] // greatest common inner
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protected[diplomacy] def gco: Option[BaseNode] // greatest common outer
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protected[diplomacy] def outputs: Seq[(BaseNode, String)]
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protected[diplomacy] def inputs: Seq[(BaseNode, String)]
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protected[diplomacy] def colour: String
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}
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case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
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(inward: InwardNode[DI, UI, BI], outward: OutwardNode[DO, UO, BO])
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extends Object with InwardNodeHandle[DI, UI, BI] with OutwardNodeHandle[DO, UO, BO]
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trait InwardNodeHandle[DI, UI, BI <: Data]
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{
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val inward: InwardNode[DI, UI, BI]
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def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] =
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inward.:=(h)(sourceInfo)
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}
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trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, UI, BI]
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{
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val inward = this
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protected[diplomacy] val numPI: Range.Inclusive
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI])]()
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private var iRealized = false
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protected[diplomacy] def iPushed = accPI.size
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protected[diplomacy] def iPush(index: Int, node: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (!noIs, s"${name}${lazyModule.line} was incorrectly connected as a sink" + info)
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require (!iRealized, s"${name}${lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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accPI += ((index, node))
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}
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private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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protected[diplomacy] lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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protected[diplomacy] val iParams: Seq[UI]
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val bundleIn: Vec[BI]
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}
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trait OutwardNodeHandle[DO, UO, BO <: Data]
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{
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val outward: OutwardNode[DO, UO, BO]
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}
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trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO, UO, BO]
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{
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val outward = this
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protected[diplomacy] val numPO: Range.Inclusive
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO])]()
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private var oRealized = false
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protected[diplomacy] def oPushed = accPO.size
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protected[diplomacy] def oPush(index: Int, node: InwardNode [DO, UO, BO])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noOs = numPO.size == 1 && numPO.contains(0)
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require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
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require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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accPO += ((index, node))
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}
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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protected[diplomacy] lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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protected[diplomacy] val oParams: Seq[DO]
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val bundleOut: Vec[BO]
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}
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class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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private val dFn: (Int, Seq[DI]) => Seq[DO],
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private val uFn: (Int, Seq[UO]) => Seq[UI],
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protected[diplomacy] val numPO: Range.Inclusive,
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protected[diplomacy] val numPI: Range.Inclusive)
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extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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// meta-data for printing the node graph
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protected[diplomacy] def colour = inner.colour
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protected[diplomacy] def outputs = oPorts.map(_._2) zip edgesOut.map(e => outer.labelO(e))
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protected[diplomacy] def inputs = iPorts.map(_._2) zip edgesIn .map(e => inner.labelI(e))
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private def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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protected[diplomacy] lazy val oParams: Seq[DO] = {
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val o = dFn(oPorts.size, iPorts.map { case (i, n) => n.oParams(i) })
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reqE(oPorts.size, o.size)
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o.map(outer.mixO(_, this))
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}
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protected[diplomacy] lazy val iParams: Seq[UI] = {
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val i = uFn(iPorts.size, oPorts.map { case (o, n) => n.iParams(o) })
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reqE(i.size, iPorts.size)
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i.map(inner.mixI(_, this))
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}
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protected[diplomacy] def gco = if (iParams.size != 1) None else inner.getO(iParams(0))
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protected[diplomacy] def gci = if (oParams.size != 1) None else outer.getI(oParams(0))
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => outer.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => inner.edgeI(n.oParams(o), i) }
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val flip = false // needed for blind nodes
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private def flipO(b: Vec[BO]) = if (flip) b.flip else b
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private def flipI(b: Vec[BI]) = if (flip) b else b.flip
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val wire = false // needed if you want to grab access to from inside a module
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private def wireO(b: Vec[BO]) = if (wire) Wire(b) else b
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private def wireI(b: Vec[BI]) = if (wire) Wire(b) else b
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lazy val bundleOut = wireO(flipO(outer.bundleO(edgesOut)))
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lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn)))
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// connects the outward part of a node with the inward part of this node
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override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
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val x = this // x := y
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val y = h.outward
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val info = sourceLine(sourceInfo, " at ", "")
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require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
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val i = x.iPushed
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val o = y.oPushed
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y.oPush(i, x)
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x.iPush(o, y)
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val (out, binding) = inner.connect(y.bundleOut(o), x.bundleIn(i), x.edgesIn(i))
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LazyModule.stack.head.bindings = binding :: LazyModule.stack.head.bindings
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out
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}
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}
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class SimpleNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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oFn: (Int, Seq[D]) => Seq[D],
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iFn: (Int, Seq[U]) => Seq[U],
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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extends MixedNode[D, U, EI, B, D, U, EO, B](imp, imp)(oFn, iFn, numPO, numPI)
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class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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extends SimpleNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
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class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override lazy val bundleIn = bundleOut
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}
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class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override lazy val bundleOut = bundleIn
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}
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class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
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{
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require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
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override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut }
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}
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class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
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{
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require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
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override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
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}
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class BlindOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, 1 to 1)
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{
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override val flip = true
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override lazy val bundleOut = bundleIn
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}
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class BlindInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO)
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, 1 to 1, 0 to 0)
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{
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override val flip = true
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override lazy val bundleIn = bundleOut
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}
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class InternalOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, 1 to 1)
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{
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override val wire = true
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override lazy val bundleOut = bundleIn
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}
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class InternalInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO)
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, 1 to 1, 0 to 0)
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{
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override val wire = true
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override lazy val bundleIn = bundleOut
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}
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class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
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extends SimpleNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
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{
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require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
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require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
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}
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