73 lines
2.0 KiB
Scala
73 lines
2.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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import rocket._
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/////
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trait L2MasterPort extends CoreplexNetwork
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{
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val module: L2MasterPortModule
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val l2in = TLInputNode()
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l1tol2.node := l2in
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}
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trait L2MasterPortBundle extends CoreplexNetworkBundle
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{
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val outer: L2MasterPort
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val l2in = outer.l2in.bundleIn
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}
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trait L2MasterPortModule extends CoreplexNetworkModule
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{
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val outer: L2MasterPort
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val io: L2MasterPortBundle
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}
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/////
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with L2MasterPort
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with RocketTiles {
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override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
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}
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with L2MasterPortBundle
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with RocketTilesBundle
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with L2MasterPortModule
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with RocketTilesModule
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/////
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with L2MasterPort
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with AsyncRocketTiles {
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override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
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}
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with L2MasterPortBundle
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with AsyncRocketTilesBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with L2MasterPortModule
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with AsyncRocketTilesModule
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