307 lines
10 KiB
Scala
307 lines
10 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package coreplex
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import Chisel._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.converters._
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import uncore.util._
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import rocket._
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import util._
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import util.ConfigUtils._
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import config._
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class BaseCoreplexConfig extends Config (
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{ (pname,site,here) =>
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lazy val innerDataBits = site(XLen)
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case PAddrBits => 32
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 7
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//Params used by all caches
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case CacheName("L1I") => CacheConfig(
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nSets = 64,
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nWays = 4,
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rowBits = site(L1toL2Config).beatBytes*8,
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nTLBEntries = 8,
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cacheIdBits = 0,
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splitMetadata = false)
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case CacheName("L1D") => CacheConfig(
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nSets = 64,
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nWays = 4,
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rowBits = site(L1toL2Config).beatBytes*8,
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nTLBEntries = 8,
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cacheIdBits = 0,
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splitMetadata = false)
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays)
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case DCacheKey => DCacheConfig(nMSHRs = 2)
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case DataScratchpadSize => 0
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//L2 Memory System Params
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case AmoAluOperandBits => site(XLen)
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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//Tile Constants
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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//Rocket Core Constants
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case CoreInstBits => if (site(UseCompressed)) 16 else 32
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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case RetireWidth => 1
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case UseVM => true
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case UseUser => false
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case UseDebug => true
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case NBreakpoints => 1
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case NPerfCounters => 0
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case NPerfEvents => 0
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case FastLoadWord => true
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case FastLoadByte => false
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case FastJAL => false
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case XLen => 64
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case FPUKey => Some(FPUConfig())
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case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
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case UseAtomics => true
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case UseCompressed => true
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case NCustomMRWCSRs => 0
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case MtvecInit => Some(BigInt(0))
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case MtvecWritable => true
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//Uncore Paramters
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
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case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */,
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nCachingClients = 1,
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nCachelessClients = 1,
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maxClientXacts = max_int(
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// L1 cache
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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}
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case BootROMFile => "./bootrom/bootrom.img"
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case NTiles => 1
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case BroadcastConfig => BroadcastConfig()
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case BankedL2Config => BankedL2Config()
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
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case EnableL2Logging => false
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case _ => throw new CDEMatchError
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}
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}
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)
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class WithNCores(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NTiles => n
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case _ => throw new CDEMatchError
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})
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class WithNBanksPerMemChannel(n: Int) extends Config(
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(pname, site, here, up) => pname match {
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case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
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case _ => throw new CDEMatchError
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})
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class WithNTrackersPerBank(n: Int) extends Config(
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(pname, site, here, up) => pname match {
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case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
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case _ => throw new CDEMatchError
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})
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// This is the number of sets **per way**
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class WithL1ICacheSets(sets: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
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case _ => throw new CDEMatchError
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})
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// This is the number of sets **per way**
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class WithL1DCacheSets(sets: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
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case _ => throw new CDEMatchError
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})
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class WithL1ICacheWays(ways: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
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case _ => throw new CDEMatchError
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})
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class WithL1DCacheWays(ways: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
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case _ => throw new CDEMatchError
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})
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class WithCacheBlockBytes(linesize: Int) extends Config(
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(pname,site,here) => pname match {
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case CacheBlockBytes => linesize
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case _ => throw new CDEMatchError
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})
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class WithDataScratchpad(n: Int) extends Config(
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(pname,site,here,up) => pname match {
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case DataScratchpadSize => n
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
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case _ => throw new CDEMatchError
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})
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// TODO: re-add L2
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case CacheName("L2") => CacheConfig(
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nSets = 1024,
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nWays = 1,
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rowBits = site(L1toL2Config).beatBytes*8,
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nTLBEntries = 0,
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cacheIdBits = 1,
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splitMetadata = false)
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case _ => throw new CDEMatchError
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})
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class WithBufferlessBroadcastHub extends Config(
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(pname, site, here, up) => pname match {
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case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
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})
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/**
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* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
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*
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* There is a very restrictive set of conditions under which the stateless
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* bridge will function properly. There can only be a single tile. This tile
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* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
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* uncached channel capable of writes (i.e. a RoCC accelerator).
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*
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* This is because the stateless bridge CANNOT generate probes, so if your
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* system depends on coherence between channels in any way,
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config(
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(pname,site,here,up) => pname match {
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/* !!! FIXME
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
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val pass = LazyModule(new TLBuffer(0))
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(pass.node, pass.node)
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})
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*/
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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class WithPLRU extends Config(
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(pname, site, here) => pname match {
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case _ => throw new CDEMatchError
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})
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class WithL2Capacity(size_kb: Int) extends Config(
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(pname,site,here) => pname match {
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case _ => throw new CDEMatchError
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})
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class WithNL2Ways(n: Int) extends Config(
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(pname,site,here,up) => pname match {
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case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
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})
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case FPUKey => Some(FPUConfig(divSqrt = false))
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case _ => throw new CDEMatchError
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})
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class WithBlockingL1 extends Config(
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(pname,site,here,up) => pname match {
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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class WithSmallCores extends Config(
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(pname,site,here,up) => pname match {
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case MulDivKey => Some(MulDivConfig())
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case FPUKey => None
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case UseVM => false
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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class WithRoccExample extends Config(
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(pname, site, here) => pname match {
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case BuildRoCC => Seq(
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RoccParameters(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
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RoccParameters(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => Module(new TranslatorExample()(p)),
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nPTWPorts = 1),
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RoccParameters(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
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case RoccMaxTaggedMemXacts => 1
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case _ => throw new CDEMatchError
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})
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class WithDefaultBtb extends Config(
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(pname,site,here) => pname match {
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case BtbKey => BtbParameters()
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case _ => throw new CDEMatchError
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})
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class WithFastMulDiv extends Config(
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(pname,site,here) => pname match {
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case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
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case _ => throw new CDEMatchError
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})
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class WithoutMulDiv extends Config(
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(pname, site, here) => pname match {
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case MulDivKey => None
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case _ => throw new CDEMatchError
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})
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class WithoutFPU extends Config(
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(pname, site, here) => pname match {
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case FPUKey => None
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case _ => throw new CDEMatchError
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})
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class WithFPUWithoutDivSqrt extends Config (
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(pname, site, here) => pname match {
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case FPUKey => Some(FPUConfig(divSqrt = false))
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case _ => throw new CDEMatchError
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})
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