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riscv
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rocket-chip
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b7181ba49b
rocket-chip
/
vsim
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Scott Johnson
2d12f6689c
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 16:55:57 -07:00
..
.gitignore
Write test harness in Chisel
2016-08-15 23:27:27 -07:00
Makefile
Write test harness in Chisel
2016-08-15 23:27:27 -07:00
Makefrag
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 16:55:57 -07:00
Makefrag-verilog
Write test harness in Chisel
2016-08-15 23:27:27 -07:00
vlsi_mem_gen
Massive update containing several months of changes from the now-defunct private chip repo.
2015-07-02 14:43:30 -07:00