| .. |
|
arbiter.scala
|
Use HeaderlessTileLinkIO
|
2015-04-13 15:58:10 -07:00 |
|
btb.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
consts.scala
|
Renamed PCR to CSR
|
2015-04-11 02:16:44 -07:00 |
|
core.scala
|
Clean up handling of icache's io.cpu.npc signal
|
2015-05-18 18:22:48 -07:00 |
|
csr.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
ctrl.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
decode.scala
|
fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
|
2015-03-10 10:28:05 -07:00 |
|
dpath_alu.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
dpath.scala
|
Renamed PCR to CSR
|
2015-04-11 02:16:44 -07:00 |
|
fpu.scala
|
Integrate divide/sqrt unit
|
2015-04-04 16:39:17 -07:00 |
|
icache.scala
|
Clean up handling of icache's io.cpu.npc signal
|
2015-05-18 18:22:48 -07:00 |
|
instructions.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
multiplier.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
nbdcache.scala
|
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
|
2015-05-30 16:25:27 +01:00 |
|
package.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
ptw.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
rocc.scala
|
HeaderlessTileLinkIO -> ClientTileLinkIO
|
2015-04-17 16:56:53 -07:00 |
|
tile.scala
|
HeaderlessTileLinkIO -> ClientTileLinkIO
|
2015-04-17 16:56:53 -07:00 |
|
tlb.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
util.scala
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
