109 lines
4.0 KiB
Scala
109 lines
4.0 KiB
Scala
package object uncore {
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import Chisel._
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import Node._
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import scala.collection.mutable.Stack
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//TODO: Remove these Networking classes from the package object once Scala bug
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//SI-3439 is resolved.
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val src = UFix(width = conf.idBits)
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val dst = UFix(width = conf.idBits)
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}
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abstract class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val header = (new PhysicalHeader)
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val payload = data
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}
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class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetworkIO()(data)(conf) {
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override def clone = { new BasicCrossbarIO()(data).asInstanceOf[this.type] }
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}
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
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class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}.flip
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val out = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}
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}
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val rdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = (new RRArbiter(conf.nEndpoints)){io.in(0).bits.clone}
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(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
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arb.valid := in.valid && (in.bits.header.dst === UFix(i))
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arb.bits := in.bits
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rdy := arb.ready && (in.bits.header.dst === UFix(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until conf.nEndpoints) {
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io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
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}
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}
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case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
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abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Component {
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override val io: Vec[TileLinkType]
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val physicalNetworks: Seq[PhysicalNetwork]
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require(endpoints.length == conf.nEndpoints)
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}
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class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val src = UFix(width = conf.idBits)
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val dst = UFix(width = conf.idBits)
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}
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object FIFOedLogicalNetworkIOWrapper {
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def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = {
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val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone }
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shim.io.in.valid := in.valid
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shim.io.in.bits := in.bits
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in.ready := shim.io.in.ready
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shim.io.out
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}
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}
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class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
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val io = new Bundle {
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val in = (new FIFOIO){ data }.flip
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val out = (new FIFOIO){(new LogicalNetworkIO){ data }}
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}
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io.out.valid := io.in.valid
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io.out.bits.payload := io.in.bits
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io.out.bits.header.dst := dst
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io.out.bits.header.src := src
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io.in.ready := io.out.ready
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}
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object FIFOedLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: FIFOIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
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val shim = (new FIFOedLogicalNetworkIOUnwrapper){ in.bits.payload.clone }
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shim.io.in.valid := in.valid
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shim.io.in.bits := in.bits
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in.ready := shim.io.in.ready
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shim.io.out
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}
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}
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class FIFOedLogicalNetworkIOUnwrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
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val io = new Bundle {
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val in = (new FIFOIO){(new LogicalNetworkIO){ data }}.flip
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val out = (new FIFOIO){ data }
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}
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io.out.valid := io.in.valid
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io.out.bits := io.in.bits.payload
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io.in.ready := io.out.ready
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}
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class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val header = new LogicalHeader
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val payload = data
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override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
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}
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}
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