51 lines
1.5 KiB
Scala
51 lines
1.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.ahb
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import Chisel._
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import config._
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import diplomacy._
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import regmapper._
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import scala.math.{min,max}
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class AHBFanout()(implicit p: Parameters) extends LazyModule {
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val node = AHBNexusNode(
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numSlavePorts = 1 to 1,
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numMasterPorts = 1 to 32,
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masterFn = { case Seq(m) => m },
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slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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// Require consistent bus widths
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val port0 = node.edgesOut(0).slave
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node.edgesOut.foreach { edge =>
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val port = edge.slave
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require (port.beatBytes == port0.beatBytes,
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s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
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}
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val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
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val in = io.in(0)
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val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _)))
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val d_sel = Reg(a_sel)
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when (in.hready) { d_sel := a_sel }
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(a_sel zip io.out) foreach { case (sel, out) =>
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out := in
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out.hsel := in.hsel && sel
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}
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in.hreadyout := !Mux1H(d_sel, io.out.map(!_.hreadyout))
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in.hresp := Mux1H(d_sel, io.out.map(_.hresp))
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in.hrdata := Mux1H(d_sel, io.out.map(_.hrdata))
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}
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}
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