3dd51ff734
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in Chisel except for some negative edge clocking requirement. - For real implementations, the AsyncDebugBusTo/From is insufficient. This commit includes cases where they are used, but because they are not reset asynchronously, a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false. - This commit differs significantly from the earlier attempt. Now, the DTM and synchronizer is instantiated within Top, as it is a real piece of hardware (vs. test infrastructure). -TestHarness takes a parameter vs. creating an entirely new TestHarness class. It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false, and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM) is true. To build Verilog which includes the JtagDTM within Top: make CONFIG=WithJtagDTM_... To test using gdb->OpenOCD->jtag_vpi->Verilog: First, install openocd (included in this commit) ./bootstrap ./configure --prefix=$OPENOCD --enable-jtag-vpi make make install Then to run a simulation: On a 32-bit core: $(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \ --run ./simv-TestHarness-WithJtagDTM_... \ --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \ --freedom-e300-sim \ SimpleRegisterTest.test_s0 On a 64-bit core: $(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \ --run ./simv-TestHarness-WithJtagDTM_... \ --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \ --freedom-u500-sim \ SimpleRegisterTest.test_s0
155 lines
3.7 KiB
Verilog
155 lines
3.7 KiB
Verilog
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module AsyncMailbox (
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// Write Interface
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enq_clock
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, enq_reset
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, enq_ready
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, enq_valid
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, enq_bits
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// Read Interface
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, deq_clock
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, deq_reset
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, deq_ready
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, deq_valid
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, deq_bits
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);
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//--------------------------------------------------------
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// Parameter Declarations
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parameter WIDTH = 64;
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//--------------------------------------------------------
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// I/O Declarations
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// Write Interface
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input enq_clock;
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wire w_clock = enq_clock;
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input enq_reset;
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wire w_reset = enq_reset;
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output enq_ready;
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wire w_ready;
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assign enq_ready = w_ready;
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input enq_valid;
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wire w_valid = enq_valid;
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input [WIDTH - 1 : 0 ] enq_bits;
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wire [WIDTH - 1 : 0 ] w_bits = enq_bits;
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// Read Interface
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input deq_clock;
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wire r_clock = deq_clock;
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input deq_reset;
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wire r_reset = deq_reset;
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output deq_valid;
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wire r_valid;
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assign deq_valid = r_valid;
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input deq_ready;
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wire r_ready = deq_ready;
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output [WIDTH - 1 : 0] deq_bits;
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wire [WIDTH - 1 : 0] r_bits;
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assign deq_bits = r_bits;
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//--------------------------------------------------------
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// FIFO Memory Declaration
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reg [WIDTH - 1 :0] mailboxReg;
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//--------------------------------------------------------
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// Reg and Wire Declarations
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wire w_full;
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wire w_fire;
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wire r_empty;
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wire r_fire;
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// Read & Write Address Pointers
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reg w_wrAddrReg;
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wire w_wrAddrNxt;
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reg r_rdAddrReg;
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wire r_rdAddrNxt;
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reg wrAddrReg_sync;
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reg rdAddrReg_sync;
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reg r_wrAddrReg;
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reg w_rdAddrReg;
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//--------------------------------------------------------
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// Reg and Wire Declarations
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assign w_full = ~(w_wrAddrReg == r_rdAddrReg);
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assign w_wrAddrNxt = ~w_wrAddrReg ;
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assign r_rdAddrNxt = ~r_rdAddrReg;
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assign r_empty = (r_wrAddrReg == r_rdAddrReg);
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assign w_ready = ~w_full;
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assign w_fire = w_ready & w_valid;
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// Read Logic
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assign r_valid = ~r_empty;
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assign r_fire = r_ready & r_valid;
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assign r_bits = mailboxReg;
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always @(posedge w_clock) begin
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if (w_fire) begin
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mailboxReg <= w_bits;
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end
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end
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//--------------------------------------------------------
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// Sequential logic
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//
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always @(posedge w_clock or posedge w_reset) begin
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if (w_reset ) begin
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w_wrAddrReg <= 1'b0;
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rdAddrReg_sync <= 1'b0;
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w_rdAddrReg <= 1'b0;
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end else begin
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if (w_fire) begin
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w_wrAddrReg <= w_wrAddrNxt;
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end
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rdAddrReg_sync <= r_rdAddrReg;
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w_rdAddrReg <= rdAddrReg_sync;
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end
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end
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always @(posedge r_clock or posedge r_reset) begin
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if (r_reset) begin
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r_rdAddrReg <= 1'b0;
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wrAddrReg_sync <= 1'b0;
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r_wrAddrReg <= 1'b0;
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end else begin
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if (r_fire) begin
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r_rdAddrReg <= r_rdAddrNxt;
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end
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wrAddrReg_sync <= w_wrAddrReg;
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r_wrAddrReg <= wrAddrReg_sync;
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end
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end // always @ (posedge r_clock)
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endmodule // AsyncMailbox
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