mwachs5 a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) ... * util: Do Set/Reset Async Registers more properly The way BlackBox "init" registers were coded before was not really kosher verilog for most synthesis tools. Also, the enable logic wasn't really pushed down into the flop. This change is more explicit about set/reset flops, again this is only a 'temporary' problem that would go away with parameterizable blackboxes (or general async reset support). * Tabs, not spaces, in Makefiles * util: Fix typos in Async BB Reg Comments		2016-09-16 13:50:09 -07:00
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.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	allow override of vlsi_mem_gen script	2016-09-06 14:44:12 -07:00
Makefrag	util: Do BlackBox Async Set/Reset Registers more properly (#305)	2016-09-16 13:50:09 -07:00
Makefrag-verilog	remove redundant verilator rule	2016-09-14 20:31:17 -07:00
vlsi_mem_gen	fix null statement in vsli_mem_gen ala firrtl#264 (#252)	2016-09-07 11:04:36 -07:00