100 lines
3.3 KiB
Scala
100 lines
3.3 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
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class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => if (supportClients) c.copy(clients = c.clients .map(_.copy(supportsHint = true))) else c },
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managerFn = { case Seq(m) => if (supportManagers) m.copy(managers = m.managers.map(_.copy(supportsHint = true))) else m })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val in = io.in(0)
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val out = io.out(0)
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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// Don't add support for clients if there is no BCE channel
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val bce = edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe
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require (!supportClients || bce)
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if (supportManagers) {
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits)) else Bool(true)
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val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
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// Prioritize existing D traffic over HintAck
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in.d.valid := out.d.valid || (bypassD && in.a.valid)
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out.d.ready := in.d.ready
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in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits))
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in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready)
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out.a.valid := in.a.valid && !bypassD
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out.a.bits := in.a.bits
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} else {
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready
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out.a.bits := in.a.bits
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in.d.valid := out.d.valid
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out.d.ready := in.d.ready
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in.d.bits := out.d.bits
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}
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if (supportClients) {
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val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source) else Bool(true)
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val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint
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// Prioritize existing C traffic over HintAck
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out.c.valid := in.c.valid || (bypassC && in.b.valid)
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in.c.ready := out.c.ready
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out.c.bits := Mux(in.c.valid, in.c.bits, edgeOut.HintAck(out.b.bits))
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out.b.ready := Mux(bypassC, out.c.ready && !in.c.valid, in.b.ready)
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in.b.valid := out.b.valid && !bypassC
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in.b.bits := out.b.bits
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} else if (bce) {
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in.b.valid := out.b.valid
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out.b.ready := in.b.ready
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in.b.bits := out.b.bits
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out.c.valid := in.c.valid
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in.c.ready := out.c.ready
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out.c.bits := in.c.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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}
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if (bce) {
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// Pass E through unchanged
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out.e.valid := in.e.valid
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in.e.ready := out.e.ready
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out.e.bits := in.e.bits
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} else {
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in.e.ready := Bool(true)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLHintHandler
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{
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// applied to the TL source node; y.node := TLHintHandler(x.node)
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def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit sourceInfo: SourceInfo): TLBaseNode = {
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val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
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hints.node := x
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hints.node
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}
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}
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