125 lines
4.2 KiB
Scala
125 lines
4.2 KiB
Scala
package Top
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{
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import Chisel._
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import Node._;
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import queues._;
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import Constants._;
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class ioMemory extends Bundle()
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{
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val mem_mrq_val = Bool('input);
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val mem_mrq_cmd = Bits(4, 'input);
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val mem_mrq_type = Bits(3, 'input);
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val mem_xsdq_rdy = Bool('output);
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val mem_xsdq_val = Bool('input);
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val mem_mrq_deq = Bool('output);
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val dpath_rs2 = Bits(64, 'input);
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val dpath_waddr = UFix(5, 'input);
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val dpath_alu_out = UFix(64, 'input);
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val dmem_req_val = Bool('output);
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val dmem_req_rdy = Bool('input);
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val dmem_req_op = Bits(4, 'output);
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val dmem_req_addr = UFix(32, 'output);
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val dmem_req_data = Bits(64, 'output);
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val dmem_req_wmask = Bits(8, 'output);
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val dmem_req_tag = Bits(12, 'output);
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}
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class rocketMemory extends Component
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{
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override val io = new ioMemory();
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val mrq_enq_xf
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= (io.mem_mrq_cmd === M_FRD || io.mem_mrq_cmd === M_FWR);
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val mrq_enq_op
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= Mux(io.mem_mrq_cmd === M_FRD, M_XRD,
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Mux(io.mem_mrq_cmd === M_FWR, M_XWR,
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io.mem_mrq_cmd));
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val mrq_enq_type = io.mem_mrq_type;
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val mrq = new queueSimplePF(45, 4, 2);
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val xsdq = new queueSimplePF(64, 4, 2);
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mrq.io.q_reset := Bool(false);
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mrq.io.enq_bits := Cat(mrq_enq_xf,mrq_enq_op,mrq_enq_type,io.dpath_waddr,io.dpath_alu_out(31,0));
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mrq.io.enq_val ^^ io.mem_mrq_val;
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// mrq.io.enq_rdy <> (); issue logic takes care of this
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val mrq_deq_xf = Wire(){Bits(width = 1)};
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val mrq_deq_op = Wire(){Bits(width = 4)};
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val mrq_deq_type = Wire(){Bits(width = 3)};
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val mrq_deq_waddr = Wire(){Bits(width = 5)};
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val mrq_deq_addr = Wire(){Bits(width = 32)};
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val mrq_deq_bits = mrq.io.deq_bits;
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mrq_deq_bits.Match(Array(mrq_deq_xf, mrq_deq_op, mrq_deq_type, mrq_deq_waddr, mrq_deq_addr));
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val mrq_deq_val = mrq.io.deq_val;
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xsdq.io.q_reset := Bool(false);
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xsdq.io.enq_bits ^^ io.dpath_rs2;
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xsdq.io.enq_val ^^ io.mem_xsdq_val;
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xsdq.io.enq_rdy ^^ io.mem_xsdq_rdy;
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val mrq_deq_flush = mrq_deq_op === M_FLA;
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val mrq_deq_load = mrq_deq_op === M_XRD;
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val mrq_deq_xstore = mrq_deq_op === M_XWR & ~mrq_deq_xf & xsdq.io.deq_val;
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val mrq_deq_rdy = io.dmem_req_rdy & (mrq_deq_load | mrq_deq_xstore | mrq_deq_flush);
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io.mem_mrq_deq := (mrq_deq_val & mrq_deq_rdy).toBool;
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mrq.io.deq_rdy := mrq_deq_rdy.toBool;
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val xsdq_deq_rdy = io.dmem_req_rdy & mrq_deq_val & mrq_deq_op === M_XWR & ~mrq_deq_xf;
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xsdq.io.deq_rdy := xsdq_deq_rdy.toBool;
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val wdata = xsdq.io.deq_bits;
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val wmask_b =
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Mux(mrq_deq_addr(2,0) === UFix(0, 3), Bits("b0000_0001", 8),
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Mux(mrq_deq_addr(2,0) === UFix(1, 3), Bits("b0000_0010", 8),
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Mux(mrq_deq_addr(2,0) === UFix(2, 3), Bits("b0000_0100", 8),
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Mux(mrq_deq_addr(2,0) === UFix(3, 3), Bits("b0000_1000", 8),
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Mux(mrq_deq_addr(2,0) === UFix(4, 3), Bits("b0001_0000", 8),
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Mux(mrq_deq_addr(2,0) === UFix(5, 3), Bits("b0010_0000", 8),
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Mux(mrq_deq_addr(2,0) === UFix(6, 3), Bits("b0100_0000", 8),
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Mux(mrq_deq_addr(2,0) === UFix(7, 3), Bits("b1000_0000", 8),
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UFix(0, 8)))))))));
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val wmask_h =
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Mux(mrq_deq_addr(2,1) === UFix(0, 2), Bits("b0000_0011", 8),
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Mux(mrq_deq_addr(2,1) === UFix(1, 2), Bits("b0000_1100", 8),
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Mux(mrq_deq_addr(2,1) === UFix(2, 2), Bits("b0011_0000", 8),
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Mux(mrq_deq_addr(2,1) === UFix(3, 2), Bits("b1100_0000", 8),
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UFix(0, 8)))));
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val wmask_w =
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Mux(mrq_deq_addr(2) === UFix(0, 1), Bits("b0000_1111", 8),
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Mux(mrq_deq_addr(2) === UFix(1, 1), Bits("b1111_0000", 8),
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UFix(0, 8)));
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val wmask_d =
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Bits("b1111_1111", 8);
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io.dmem_req_val := (mrq_deq_val & (mrq_deq_load | mrq_deq_xstore | mrq_deq_flush)).toBool;
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io.dmem_req_op := mrq_deq_op;
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io.dmem_req_addr := Cat(mrq_deq_addr(31,3), UFix(0, 3)).toUFix;
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io.dmem_req_data :=
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Mux(mrq_deq_type === MT_B, Fill(8, wdata( 7,0)),
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Mux(mrq_deq_type === MT_H, Fill(4, wdata(15,0)),
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Mux(mrq_deq_type === MT_W, Fill(2, wdata(31,0)),
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Mux(mrq_deq_type === MT_D, wdata,
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UFix(0, 64)))));
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io.dmem_req_wmask :=
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Mux(mrq_deq_type === MT_B, wmask_b,
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Mux(mrq_deq_type === MT_H, wmask_h,
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Mux(mrq_deq_type === MT_W, wmask_w,
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Mux(mrq_deq_type === MT_D, wmask_d,
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UFix(0, 8)))));
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io.dmem_req_tag := Cat(mrq_deq_xf,mrq_deq_type,mrq_deq_addr(2,0),mrq_deq_waddr);
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}
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}
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