40 lines
1.5 KiB
Scala
40 lines
1.5 KiB
Scala
// See LICENSE for license details.
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package uncore
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package constants
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import Chisel._
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object MemoryOpConstants extends MemoryOpConstants
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trait MemoryOpConstants {
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val NUM_XA_OPS = 9
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val M_SZ = 5
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val M_X = BitPat("b?????");
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val M_XRD = UInt("b00000"); // int load
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val M_XWR = UInt("b00001"); // int store
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val M_PFR = UInt("b00010"); // prefetch with intent to read
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val M_PFW = UInt("b00011"); // prefetch with intent to write
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val M_XA_SWAP = UInt("b00100");
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val M_FLUSH_ALL = UInt("b00101") // flush all lines
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val M_XLR = UInt("b00110");
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val M_XSC = UInt("b00111");
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val M_XA_ADD = UInt("b01000");
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val M_XA_XOR = UInt("b01001");
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val M_XA_OR = UInt("b01010");
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val M_XA_AND = UInt("b01011");
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val M_XA_MIN = UInt("b01100");
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val M_XA_MAX = UInt("b01101");
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val M_XA_MINU = UInt("b01110");
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val M_XA_MAXU = UInt("b01111");
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val M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
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val M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
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val M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
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def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
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def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
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def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
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def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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}
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