riscv/rocket-chip
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rocket-chip/src/main/scala/coreplex
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Wesley W. Terpstra 19eb9b6906 l1tol2: put a flow Q on the exits (#606) 
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
..
BaseCoreplex.scala rocket: use diplomatic interrupts 2017-03-02 21:19:23 -08:00
Configs.scala WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Coreplex.scala rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
CoreplexNetwork.scala l1tol2: put a flow Q on the exits (#606) 2017-03-23 16:28:32 -07:00
RISCVPlatform.scala diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
RocketTiles.scala coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00