135 lines
3.9 KiB
Scala
135 lines
3.9 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import scala.math._
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class IOTLBPTW extends Bundle {
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val req = new FIFOIO()(UFix(width = VPN_BITS))
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val resp = new PipeIO()(new Bundle {
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val error = Bool()
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val ppn = UFix(width = PPN_BITS)
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val perm = Bits(width = PERM_BITS)
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}).flip
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val status = Bits(INPUT, width = 32)
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val invalidate = Bool(INPUT)
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}
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class IODatapathPTW extends Bundle {
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val ptbr = UFix(INPUT, PADDR_BITS)
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val invalidate = Bool(INPUT)
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val status = Bits(INPUT, 32)
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}
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class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
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{
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val io = new Bundle {
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val requestor = Vec(n) { new IOTLBPTW }.flip
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val mem = new ioHellaCache()(conf.dcache)
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val dpath = new IODatapathPTW
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}
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val levels = 3
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val bitsPerLevel = VPN_BITS/levels
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require(VPN_BITS == levels * bitsPerLevel)
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val count = Reg() { UFix(width = log2Up(levels)) }
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val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UFix() };
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val state = Reg(resetVal = s_ready);
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val r_req_vpn = Reg() { Bits() }
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val r_req_dest = Reg() { Bits() }
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val req_addr = Reg() { UFix() }
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val r_resp_ppn = Reg() { Bits() };
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val r_resp_perm = Reg() { Bits() };
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val vpn_idxs = (1 until levels).map(i => r_req_vpn((levels-i)*bitsPerLevel-1, (levels-i-1)*bitsPerLevel))
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val vpn_idx = (2 until levels).foldRight(vpn_idxs(0))((i,j) => Mux(count === UFix(i-1), vpn_idxs(i-1), j))
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val arb = new RRArbiter(n)(UFix(width = VPN_BITS))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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when (arb.io.out.fire()) {
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r_req_vpn := arb.io.out.bits
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r_req_dest := arb.io.chosen
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req_addr := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), arb.io.out.bits(VPN_BITS-1,VPN_BITS-bitsPerLevel), UFix(0,3))
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}
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val dmem_resp_val = Reg(io.mem.resp.valid, resetVal = Bool(false))
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when (dmem_resp_val) {
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req_addr := Cat(io.mem.resp.bits.data_subword(PADDR_BITS-1, PGIDX_BITS), vpn_idx, UFix(0,3)).toUFix
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r_resp_perm := io.mem.resp.bits.data_subword(9,4);
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r_resp_ppn := io.mem.resp.bits.data_subword(PADDR_BITS-1, PGIDX_BITS);
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}
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io.mem.req.valid := state === s_req
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := M_XRD
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.kill := Bool(false)
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val resp_val = state === s_done || state === s_error
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val resp_err = state === s_error || state === s_wait
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val resp_ptd = io.mem.resp.bits.data_subword(1,0) === Bits(1)
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val resp_pte = io.mem.resp.bits.data_subword(1,0) === Bits(2)
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val resp_ppns = (0 until levels-1).map(i => Cat(r_resp_ppn(PPN_BITS-1, VPN_BITS-bitsPerLevel*(i+1)), r_req_vpn(VPN_BITS-1-bitsPerLevel*(i+1), 0)))
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val resp_ppn = (0 until levels-1).foldRight(r_resp_ppn)((i,j) => Mux(count === UFix(i), resp_ppns(i), j))
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for (i <- 0 until io.requestor.size) {
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val me = r_req_dest === UFix(i)
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io.requestor(i).resp.valid := resp_val && me
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io.requestor(i).resp.bits.error := resp_err
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io.requestor(i).resp.bits.perm := r_resp_perm
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io.requestor(i).resp.bits.ppn := resp_ppn.toUFix
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io.requestor(i).invalidate := io.dpath.invalidate
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io.requestor(i).status := io.dpath.status
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}
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// control state machine
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switch (state) {
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is (s_ready) {
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when (arb.io.out.valid) {
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state := s_req;
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}
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count := UFix(0)
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}
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is (s_req) {
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when (io.mem.req.ready) {
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state := s_wait;
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}
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}
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is (s_wait) {
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when (io.mem.resp.bits.nack) {
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state := s_req
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}
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when (dmem_resp_val) {
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when (resp_pte) { // page table entry
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state := s_done
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}
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.otherwise {
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count := count + UFix(1)
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when (resp_ptd && count < UFix(levels-1)) {
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state := s_req
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}
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.otherwise {
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state := s_error
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}
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}
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}
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}
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is (s_done) {
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state := s_ready;
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}
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is (s_error) {
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state := s_ready;
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}
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}
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}
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