Howard Mao 18ffe7b1ec don't use +verbose in vsim .run rule

2016-05-04 23:01:14 -07:00

..

.gitignore

update for rocket-chip release

2014-08-31 20:26:55 -07:00

Makefile

Add CHISEL_VERSION make argument

2016-03-24 12:00:13 -07:00

Makefrag

WIP on new memory map

2016-04-27 14:57:54 -07:00

Makefrag-verilog

don't use +verbose in vsim .run rule

2016-05-04 23:01:14 -07:00

vlsi_mem_gen

Massive update containing several months of changes from the now-defunct private chip repo.

2015-07-02 14:43:30 -07:00