90 lines
2.8 KiB
Scala
90 lines
2.8 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import scala.math._
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class ioMemSerialized(w: Int) extends Bundle
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{
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val req = (new ioDecoupled) { Bits(width = w) }
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val resp = (new ioPipe) { Bits(width = w) }.flip
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}
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class MemSerdes(w: Int) extends Component
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{
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val io = new Bundle {
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val wide = new ioMem().flip
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val narrow = new ioMemSerialized(w)
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}
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val abits = io.wide.req_cmd.bits.toBits.getWidth
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val dbits = io.wide.req_data.bits.toBits.getWidth
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val rbits = io.wide.resp.bits.getWidth
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val out_buf = Reg() { Bits() }
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val in_buf = Reg() { Bits() }
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val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(5) { UFix() }
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val state = Reg(resetVal = s_idle)
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val send_cnt = Reg(resetVal = UFix(0, log2up(max(abits, dbits))))
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val data_send_cnt = Reg(resetVal = UFix(0, log2up(MEM_DATA_BITS)))
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val adone = io.narrow.req.ready && send_cnt === UFix((abits-1)/w)
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val ddone = io.narrow.req.ready && send_cnt === UFix((dbits-1)/w)
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when (state === s_idle) {
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when (io.wide.req_cmd.valid) {
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state := Mux(io.wide.req_cmd.bits.rw, s_write_addr, s_read_addr)
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}
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}
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when (state === s_read_addr && adone) {
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state := s_idle
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send_cnt := UFix(0)
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}
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when (state === s_write_addr && adone) {
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state := s_write_idle
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send_cnt := UFix(0)
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}
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when (state === s_write_idle && io.wide.req_data.valid) {
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state := s_write_data
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}
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when (state === s_write_data && ddone) {
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data_send_cnt := data_send_cnt + UFix(1)
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state := Mux(data_send_cnt === UFix(REFILL_CYCLES-1), s_idle, s_write_idle)
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}
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when (io.narrow.req.valid && io.narrow.req.ready) {
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send_cnt := Mux(adone, UFix(0), send_cnt + UFix(1))
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out_buf := out_buf >> UFix(w)
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}
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when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
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out_buf := io.wide.req_cmd.bits.toBits
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}
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when (io.wide.req_data.valid && io.wide.req_data.ready) {
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out_buf := io.wide.req_data.bits.toBits
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}
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io.wide.req_cmd.ready := state === s_idle
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io.wide.req_data.ready := state === s_write_idle
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io.narrow.req.valid := state === s_read_addr || state === s_write_addr || state === s_write_data
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io.narrow.req.bits := out_buf
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val recv_cnt = Reg() { UFix(width = log2up(rbits)) }
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val data_recv_cnt = Reg(resetVal = UFix(0, log2up(MEM_DATA_BITS)))
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val resp_val = Reg(resetVal = Bool(false))
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resp_val := Bool(false)
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when (io.narrow.resp.valid) {
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recv_cnt := recv_cnt + UFix(1)
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when (recv_cnt === UFix((rbits-1)/w)) {
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recv_cnt := UFix(0)
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data_recv_cnt := data_recv_cnt + UFix(1)
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resp_val := Bool(true)
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}
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in_buf := Cat(io.narrow.resp.bits, in_buf(rbits-1,w))
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}
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io.wide.resp.valid := resp_val
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io.wide.resp.bits.tag := in_buf(io.wide.resp.bits.tag.width-1,0)
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io.wide.resp.bits.data := in_buf >> UFix(io.wide.resp.bits.tag.width)
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}
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