67 lines
2.4 KiB
Scala
67 lines
2.4 KiB
Scala
package uncore.devices
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.util._
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import cde.{Parameters, Field}
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class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new ClientUncachedTileLinkIO().flip
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val acq = Queue(io.acquire, 1)
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val single_beat = acq.bits.isBuiltInType(Acquire.getType)
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val multi_beat = acq.bits.isBuiltInType(Acquire.getBlockType)
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assert(!acq.valid || single_beat || multi_beat, "unsupported ROMSlave operation")
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val addr_beat = Reg(UInt())
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when (io.grant.fire()) { addr_beat := addr_beat + UInt(1) }
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when (io.acquire.fire()) { addr_beat := io.acquire.bits.addr_beat }
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val byteWidth = tlDataBits / 8
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val rows = (contents.size + byteWidth - 1)/byteWidth
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val rom = Vec.tabulate(rows) { i =>
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val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
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}
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val raddr = Cat(acq.bits.addr_block, addr_beat)
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val rdata = rom(if (rows == 1) UInt(0) else raddr(log2Up(rom.size)-1,0))
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val last = !multi_beat || addr_beat === UInt(tlDataBeats-1)
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io.grant.valid := acq.valid
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acq.ready := io.grant.ready && last
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = addr_beat,
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data = rdata)
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}
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class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
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val io = new NastiIO().flip
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val ar = Queue(io.ar, 1)
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// This assumes ROMs are in read-only parts of the address map.
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// Reuse b_queue code from NastiErrorSlave if this assumption is bad.
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when (ar.valid) { assert(ar.bits.len === UInt(0), "Can't burst-read from NastiROM") }
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assert(!(io.aw.valid || io.w.valid), "Can't write to NastiROM")
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io.aw.ready := Bool(false)
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io.w.ready := Bool(false)
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io.b.valid := Bool(false)
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val byteWidth = io.r.bits.nastiXDataBits / 8
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val rows = (contents.size + byteWidth - 1)/byteWidth
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val rom = Vec.tabulate(rows) { i =>
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val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
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}
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val rdata = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
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io.r <> ar
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io.r.bits := NastiReadDataChannel(ar.bits.id, rdata)
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}
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