116 lines
4.2 KiB
Scala
116 lines
4.2 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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import scala.collection.mutable.ListBuffer
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import scala.math.max
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// A potentially empty half-open range; [start, end)
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case class IntRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (start <= end)
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def size = end - start
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def overlaps(x: IntRange) = start < x.end && x.start < end
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def offset(x: Int) = IntRange(x+start, x+end)
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}
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object IntRange
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{
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implicit def apply(end: Int): IntRange = apply(0, end)
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}
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case class IntSourceParameters(
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range: IntRange,
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSinkParameters(
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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{
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val num = sources.map(_.range.size).sum
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// The interrupts mapping must not overlap
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sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
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// The interrupts must perfectly cover the range
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require (sources.map(_.range.end).max == num)
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}
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case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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{
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def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
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if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
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Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
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}
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def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
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require (!ei.isEmpty)
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Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip
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}
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def colour = "#0000ff" // blue
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def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => {
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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})
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}
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override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters =
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pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters =
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pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntIdentityNode() extends IdentityNode(IntImp)
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case class IntOutputNode() extends OutputNode(IntImp)
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case class IntInputNode() extends InputNode(IntImp)
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case class IntSourceNode(num: Int) extends SourceNode(IntImp)(
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IntSourcePortParameters(Seq(IntSourceParameters(num))), (if (num == 0) 0 else 1) to 1)
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case class IntSinkNode() extends SinkNode(IntImp)(
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IntSinkPortParameters(Seq(IntSinkParameters())))
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case class IntAdapterNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
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numSourcePorts: Range.Inclusive = 1 to 1,
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numSinkPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
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class IntXbar extends LazyModule
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{
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val intnode = IntAdapterNode(
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numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
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numSinkPorts = 1 to 128,
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
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sourceFn = { seq =>
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IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten)
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})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = intnode.bundleIn
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val out = intnode.bundleOut
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}
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val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten
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io.out.foreach { _ := cat }
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}
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}
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