248 lines
8.7 KiB
Scala
248 lines
8.7 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package rocket
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import Chisel._
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import config._
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import coreplex._
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import diplomacy._
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import tile._
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import uncore.devices._
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import uncore.tilelink2._
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import util._
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case class RocketTileParams(
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core: RocketCoreParams = RocketCoreParams(),
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icache: Option[ICacheParams] = Some(ICacheParams()),
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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rocc: Seq[RoCCParams] = Nil,
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btb: Option[BTBParams] = Some(BTBParams()),
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dataScratchpadBytes: Int = 0) extends TileParams {
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require(icache.isDefined)
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require(dcache.isDefined)
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}
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class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
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with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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val device = new Device {
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def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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def ofStr(x: String) = Seq(ResourceString(x))
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def describe(resources: ResourceBindings): Description = {
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val block = p(CacheBlockBytes)
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val m = if (rocketParams.core.mulDiv.nonEmpty) "m" else ""
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val a = if (rocketParams.core.useAtomics) "a" else ""
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val f = if (rocketParams.core.fpu.nonEmpty) "f" else ""
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val d = if (rocketParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
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val c = if (rocketParams.core.useCompressed) "c" else ""
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val s = if (rocketParams.core.useVM) "s" else ""
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val isa = s"rv${p(XLen)}i$m$a$f$d$c$s"
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val dcache = rocketParams.dcache.map(d => Map(
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"d-cache-block-size" -> ofInt(block),
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"d-cache-sets" -> ofInt(d.nSets),
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"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
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val icache = rocketParams.icache.map(i => Map(
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"i-cache-block-size" -> ofInt(block),
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"i-cache-sets" -> ofInt(i.nSets),
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"i-cache-size" -> ofInt(i.nSets * i.nWays * block))).getOrElse(Map())
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val dtlb = rocketParams.dcache.filter(_ => rocketParams.core.useVM).map(d => Map(
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"d-tlb-size" -> ofInt(d.nTLBEntries),
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"d-tlb-sets" -> ofInt(1))).getOrElse(Map())
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val itlb = rocketParams.icache.filter(_ => rocketParams.core.useVM).map(i => Map(
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"i-tlb-size" -> ofInt(i.nTLBEntries),
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"i-tlb-sets" -> ofInt(1))).getOrElse(Map())
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val mmu = if (!rocketParams.core.useVM) Map() else Map(
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"tlb-split" -> Nil,
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"mmu-type" -> ofStr(p(PgLevels) match {
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case 2 => "riscv,sv32"
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case 3 => "riscv,sv39"
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case 4 => "riscv,sv48"
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}))
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// Find all the caches
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val outer = masterNode.edgesOut
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.flatMap(_.manager.managers)
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.filter(_.supportsAcquireB)
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.flatMap(_.resources.headOption)
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.map(_.owner.label)
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.distinct
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val nextlevel: Option[(String, Seq[ResourceValue])] =
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if (outer.isEmpty) None else
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Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
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Description(s"cpus/cpu@${hartid}", Map(
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"reg" -> resources("reg").map(_.value),
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"device_type" -> ofStr("cpu"),
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"compatible" -> ofStr("riscv"),
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"status" -> ofStr("okay"),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"riscv,isa" -> ofStr(isa),
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"interrupt-controller" -> Nil,
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"#interrupt-cells" -> ofInt(1))
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
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}
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}
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ResourceBinding {
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Resource(device, "reg").bind(ResourceInt(BigInt(hartid)))
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intNode.edgesIn.flatMap(_.source.sources).map { case s =>
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for (i <- s.range.start until s.range.end) {
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csrIntMap.lift(i).foreach { j =>
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s.resources.foreach { r =>
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r.bind(device, ResourceInt(j))
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}
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}
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}
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}
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}
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override lazy val module = new RocketTileModule(this)
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}
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with CanHaveScratchpadBundle
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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with CanHaveLegacyRoccsModule
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with CanHaveScratchpadModule {
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require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits)
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val core = Module(p(BuildCore)(outer.p))
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decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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core.io.hartid := io.hartid // Pass through the hartid
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.resetVector := io.resetVector
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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core.io.ptw <> ptw.io.dpath
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outer.legacyRocc foreach { lr =>
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lr.module.io.core.cmd <> core.io.rocc.cmd
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lr.module.io.core.exception := core.io.rocc.exception
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core.io.rocc.resp <> lr.module.io.core.resp
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core.io.rocc.busy := lr.module.io.core.busy
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core.io.rocc.interrupt := lr.module.io.core.interrupt
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}
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// TODO eliminate this redundancy
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val h = dcachePorts.size
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val c = core.dcacheArbPorts
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val o = outer.nDCachePorts
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require(h == c, s"port list size was $h, core expected $c")
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require(h == o, s"port list size was $h, outer counted $o")
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// TODO figure out how to move the below into their respective mix-ins
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dcacheArb.io.requestor <> dcachePorts
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ptw.io.requestor <> ptwPorts
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}
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class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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val rocket = LazyModule(new RocketTile(rtp, hartid))
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val masterNode = TLOutputNode()
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masterNode :=* rocket.masterNode
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val slaveNode = TLInputNode()
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rocket.slaveNode :*= slaveNode
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val intNode = IntInputNode()
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// Some interrupt sources may be completely asynchronous, even
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// if tlClk and coreClk are the same (e.g. Debug Interrupt, which
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// is coming directly from e.g. TCK)
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val xing = LazyModule(new IntXing(3))
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rocket.intNode := xing.intnode
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xing.intnode := intNode
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val master = masterNode.bundleOut
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val slave = slaveNode.bundleIn
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val interrupts = intNode.bundleIn
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val hartid = UInt(INPUT, p(XLen))
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val resetVector = UInt(INPUT, p(XLen))
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}
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// signals that do not change:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.resetVector := io.resetVector
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}
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}
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class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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val rocket = LazyModule(new RocketTile(rtp, hartid))
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val masterNode = TLAsyncOutputNode()
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val source = LazyModule(new TLAsyncCrossingSource)
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source.node :=* rocket.masterNode
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masterNode :=* source.node
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val slaveNode = TLAsyncInputNode()
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val sink = LazyModule(new TLAsyncCrossingSink)
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rocket.slaveNode :*= sink.node
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sink.node :*= slaveNode
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val intNode = IntInputNode()
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val xing = LazyModule(new IntXing(3))
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rocket.intNode := xing.intnode
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xing.intnode := intNode
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val master = masterNode.bundleOut
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val slave = slaveNode.bundleIn
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val interrupts = intNode.bundleIn
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val hartid = UInt(INPUT, p(XLen))
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val resetVector = UInt(INPUT, p(XLen))
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}
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// signals that do not change:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.resetVector := io.resetVector
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}
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}
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class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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val rocket = LazyModule(new RocketTile(rtp, hartid))
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val masterNode = TLRationalOutputNode()
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val source = LazyModule(new TLRationalCrossingSource)
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source.node :=* rocket.masterNode
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masterNode :=* source.node
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val slaveNode = TLRationalInputNode()
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val sink = LazyModule(new TLRationalCrossingSink(util.SlowToFast))
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rocket.slaveNode :*= sink.node
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sink.node :*= slaveNode
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val intNode = IntInputNode()
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// Some interrupt sources may be completely asynchronous, even
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// if tlClk and coreClk are related (e.g. Debug Interrupt, which
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// is coming directly from e.g. TCK)
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val xing = LazyModule(new IntXing(3))
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rocket.intNode := xing.intnode
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xing.intnode := intNode
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val master = masterNode.bundleOut
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val slave = slaveNode.bundleIn
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val interrupts = intNode.bundleIn
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val hartid = UInt(INPUT, p(XLen))
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val resetVector = UInt(INPUT, p(XLen))
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}
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// signals that do not change:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.resetVector := io.resetVector
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}
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}
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