4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
36 lines
1.1 KiB
Scala
36 lines
1.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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object CRC
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{
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// A divisor of 0x1d5 is interpretted to be x^8 + x^7 + x^6 + x^4 + x^2 + 1
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// Let n be the highest term in the divisor; n=8 in 0x1d5.
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// Then, this function calculates c mod d, returning an n-bit UInt.
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// coefficient.width must be <= width
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def apply(divisor: BigInt, coefficient: UInt, width: Integer): UInt = {
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require (divisor > 0 && divisor.testBit(0))
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require (width > 0)
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assert (coefficient >> width === UInt(0))
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val n = log2Floor(divisor)
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val m = width
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if (m <= n) return coefficient
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// Initialize the reduction matrix
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val array = Array.tabulate(m) { BigInt(1) << _ }
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// Reduce the matrix of terms larger than n
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for {
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i <- (n until m).reverse
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j <- 0 to n
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if divisor.testBit(j)
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} array(i-(n-j)) ^= array(i)
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// Construct the circuit
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Cat(Seq.tabulate(n) { i => (UInt(array(i)) & coefficient).xorR } .reverse)
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}
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// Find more great CRC polynomials here: https://users.ece.cmu.edu/~koopman/crc/
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val CRC_16F_4_2 = BigInt(0x1a2eb) // HD=4 for <32751 bits and HD=6 for <93 bits
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}
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