a031686763
* util: Do Set/Reset Async Registers more properly The way BlackBox "init" registers were coded before was not really kosher verilog for most synthesis tools. Also, the enable logic wasn't really pushed down into the flop. This change is more explicit about set/reset flops, again this is only a 'temporary' problem that would go away with parameterizable blackboxes (or general async reset support). * Tabs, not spaces, in Makefiles * util: Fix typos in Async BB Reg Comments
95 lines
2.7 KiB
Plaintext
95 lines
2.7 KiB
Plaintext
#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
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$(base_dir)/vsrc/jtag_vpi.v \
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$(base_dir)/vsrc/AsyncMailbox.v \
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$(base_dir)/vsrc/AsyncResetReg.v \
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$(base_dir)/vsrc/AsyncSetReg.v \
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$(base_dir)/vsrc/ClockDivider.v \
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$(base_dir)/vsrc/ClockToSignal.v \
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$(base_dir)/vsrc/SignalToClock.v \
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
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$(generated_dir)/consts.$(CONFIG).vh \
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$(base_dir)/vsrc/$(TB).v \
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$(base_dir)/vsrc/SimDTM.v \
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$(bb_vsrcs)
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/SimDTM.cc \
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$(base_dir)/csrc/jtag_vpi.c
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#--------------------------------------------------------------------
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# Build Verilog
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#--------------------------------------------------------------------
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verilog: $(sim_vsrcs)
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.PHONY: verilog
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
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$(RISCV)/lib/libfesvr.so \
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-sverilog \
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+incdir+$(generated_dir) \
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+define+MODEL=$(MODEL) \
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+libext+.v \
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VCS_OPTS += +vpi
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VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab
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VCS_OPTS += -CC "-DVCS_VPI"
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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-debug_pp \
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simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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