c5838dd9b3
Until recently, we were assuming that the data channel in AXI was always right-justified. However, for narrow writes, the data must actually be aligned within the byte lanes. This commit changes some of the converters in order to fix this issue. There was a bug in the L2 cache in which a merged get request was causing the tracker to read the old data from the data array, overwriting the updated data acquired from outer memory. Changed it so that pending_reads is no longer set if the data in the buffer is already valid. There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and FinishToDst types used client_id for routing to managers. This caused bits to get cut off, which meant the Finish messages could not be routed correctly. Changed to use manager_id instead.
147 lines
3.0 KiB
C++
147 lines
3.0 KiB
C++
// See LICENSE for license details.
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#ifndef MM_EMULATOR_H
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#define MM_EMULATOR_H
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#include <stdint.h>
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#include <cstring>
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#include <queue>
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class mm_t
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{
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public:
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mm_t() : data(0), size(0) {}
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virtual void init(size_t sz, int word_size, int line_size);
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virtual bool ar_ready() = 0;
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virtual bool aw_ready() = 0;
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virtual bool w_ready() = 0;
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virtual bool b_valid() = 0;
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virtual uint64_t b_resp() = 0;
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virtual uint64_t b_id() = 0;
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virtual bool r_valid() = 0;
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virtual uint64_t r_resp() = 0;
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virtual uint64_t r_id() = 0;
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virtual void *r_data() = 0;
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virtual bool r_last() = 0;
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virtual void tick
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(
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bool ar_valid,
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uint64_t ar_addr,
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uint64_t ar_id,
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uint64_t ar_size,
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uint64_t ar_len,
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bool aw_valid,
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uint64_t aw_addr,
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uint64_t aw_id,
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uint64_t aw_size,
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uint64_t aw_len,
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bool w_valid,
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uint64_t w_strb,
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void *w_data,
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bool w_last,
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bool r_ready,
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bool b_ready
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) = 0;
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virtual void* get_data() { return data; }
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virtual size_t get_size() { return size; }
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virtual size_t get_word_size() { return word_size; }
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virtual size_t get_line_size() { return line_size; }
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void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size);
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std::vector<char> read(uint64_t addr);
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virtual ~mm_t();
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protected:
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uint8_t* data;
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size_t size;
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int word_size;
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int line_size;
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};
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struct mm_rresp_t
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{
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uint64_t id;
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std::vector<char> data;
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bool last;
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mm_rresp_t(uint64_t id, std::vector<char> data, bool last)
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{
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this->id = id;
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this->data = data;
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this->last = last;
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}
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mm_rresp_t()
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{
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this->id = 0;
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this->last = false;
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}
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};
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class mm_magic_t : public mm_t
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{
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public:
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mm_magic_t() : store_inflight(false) {}
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virtual void init(size_t sz, int word_size, int line_size);
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virtual bool ar_ready() { return true; }
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virtual bool aw_ready() { return !store_inflight; }
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virtual bool w_ready() { return store_inflight; }
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virtual bool b_valid() { return !bresp.empty(); }
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virtual uint64_t b_resp() { return 0; }
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virtual uint64_t b_id() { return b_valid() ? bresp.front() : 0; }
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virtual bool r_valid() { return !rresp.empty(); }
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virtual uint64_t r_resp() { return 0; }
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virtual uint64_t r_id() { return r_valid() ? rresp.front().id: 0; }
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virtual void *r_data() { return r_valid() ? &rresp.front().data[0] : &dummy_data[0]; }
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virtual bool r_last() { return r_valid() ? rresp.front().last : false; }
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virtual void tick
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(
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bool ar_valid,
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uint64_t ar_addr,
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uint64_t ar_id,
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uint64_t ar_size,
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uint64_t ar_len,
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bool aw_valid,
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uint64_t aw_addr,
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uint64_t aw_id,
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uint64_t aw_size,
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uint64_t aw_len,
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bool w_valid,
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uint64_t w_strb,
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void *w_data,
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bool w_last,
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bool r_ready,
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bool b_ready
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);
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protected:
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bool store_inflight;
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uint64_t store_addr;
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uint64_t store_id;
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uint64_t store_size;
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uint64_t store_count;
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std::vector<char> dummy_data;
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std::queue<uint64_t> bresp;
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std::queue<mm_rresp_t> rresp;
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uint64_t cycle;
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};
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void load_mem(void** mems, const char* fn, int line_size, int nchannels);
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#endif
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