112 lines
3.6 KiB
Scala
112 lines
3.6 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import rocket._
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import coreplex._
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// the following parameters will be refactored properly with TL2
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case object GlobalAddrMap extends Field[AddrMap]
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case object NCoreplexExtClients extends Field[Int]
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Bool]
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abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val q: Parameters) extends LazyModule {
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// Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2
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val pBusMasters = new RangeManager
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lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers)
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val coreplex : C = LazyModule(_coreplex(q.alterPartial {
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case NCoreplexExtClients => pBusMasters.sum
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case GlobalAddrMap => legacyAddrMap
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}))
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TopModule.contents = Some(this)
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}
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abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](_outer: L) extends Bundle {
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val outer = _outer
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}
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abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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/** Base Top with no Periphery */
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trait TopNetwork extends HasPeripheryParameters {
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this: BareTop[BaseCoreplex] =>
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implicit val p = q
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TLImp.emitMonitors = p(TLEmitMonitors)
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// Add a SoC and peripheral bus
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val socBus = LazyModule(new TLXbar)
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val peripheryBus = LazyModule(new TLXbar)
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val intBus = LazyModule(new IntXbar)
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peripheryBus.node :=
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TLWidthWidget(p(SOCBusKey).beatBytes)(
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TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
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socBus.node))
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}
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trait TopNetworkBundle extends HasPeripheryParameters {
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this: BareTopBundle[BareTop[BaseCoreplex]] =>
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implicit val p = outer.q
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val success = Bool(OUTPUT)
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}
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trait TopNetworkModule extends HasPeripheryParameters {
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this: {
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val outer: BareTop[BaseCoreplex] with TopNetwork
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val io: TopNetworkBundle
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} =>
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implicit val p = outer.p
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val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
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val coreplexSlave: Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
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val coreplexDebug: DebugBusIO = Wire(outer.coreplex.module.io.debug)
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val coreplexRtc : Bool = Wire(outer.coreplex.module.io.rtcTick)
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io.success := outer.coreplex.module.io.success
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outer.coreplex.module.io.rtcTick := coreplexRtc
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coreplexRtc := Counter(p(rocketchip.RTCPeriod)).inc()
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}
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/** Base Top with no Periphery */
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class BaseTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BareTop(_coreplex)
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with TopNetwork {
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override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
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}
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class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundle(_outer)
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with TopNetworkBundle
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class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with TopNetworkModule
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trait DirectConnection {
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this: BareTop[BaseCoreplex] with TopNetwork =>
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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}
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trait DirectConnectionModule {
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this: TopNetworkModule {
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val outer: BaseTop[BaseCoreplex]
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} =>
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coreplexMem <> outer.coreplex.module.io.mem
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outer.coreplex.module.io.slave <> coreplexSlave
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outer.coreplex.module.io.debug <> coreplexDebug
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}
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